Re: [PATCH v4 2/5] dt-bindings: pci: cadence: Extend compatible for new EP configurations

Hans Zhang
2025-04-25T16:47:39Z

On 2025/4/26 00:21, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
>
> On 25/04/2025 17:33, Hans Zhang wrote:
>>
>>
>> On 2025/4/25 22:48, Conor Dooley wrote:
>>> On Fri, Apr 25, 2025 at 02:19:11AM +0000, Manikandan Karunakaran Pillai wrote:
>>>>>
>>>>> On Thu, Apr 24, 2025 at 04:29:35PM +0100, Conor Dooley wrote:
>>>>>> On Thu, Apr 24, 2025 at 09:04:41AM +0800,hans.zhang@cixtech.com wrote:
>>>>>>> From: Manikandan K Pillai<mpillai@cadence.com>
>>>>>>>
>>>>>>> Document the compatible property for HPA (High Performance
>>>>> Architecture)
>>>>>>> PCIe controller EP configuration.
>>>>>> Please explain what makes the new architecture sufficiently different
>>>>>> from the existing one such that a fallback compatible does not work.
>>>>>>
>>>>>> Same applies to the other binding patch.
>>>>> Additionally, since this IP is likely in use on your sky1 SoC, why is a
>>>>> soc-specific compatible for your integration not needed?
>>>>>
>>>> The sky1 SoC support patches will be developed and submitted by the Sky1
>>>> team separately.
>>> Why? Cixtech sent this patchset, they should send it with their user.
>>
>> Hi Conor,
>>
>> Please look at the communication history of this website.
>>
>> https://patchwork.kernel.org/project/linux-pci/patch/CH2PPF4D26F8E1C1CBD2A866C59AA55CD7AA2A12@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/
>
> And in that thread I asked for Soc specific compatible. More than once.
> Conor asks again.
>
> I don't understand your answers at all.

Dear Krzysztof,

I'm very sorry. Due to the environmental issue of Manikandan sending
patches, I just want to express that I'm forwarding the patches for
Manikandan. Some parts were developed together by us and verified by me.

Please also ask Manikandan to reply to Conor and Krzysztof's questions.

Best regards,
Hans