Re: [PATCH v4 2/5] dt-bindings: pci: cadence: Extend compatible for new EP configurations

Conor Dooley
2025-04-25T14:48:36Z

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On Fri, Apr 25, 2025 at 02:19:11AM +0000, Manikandan Karunakaran Pillai wrote:
> >
> >
> >On Thu, Apr 24, 2025 at 04:29:35PM +0100, Conor Dooley wrote:
> >> On Thu, Apr 24, 2025 at 09:04:41AM +0800, hans.zhang@cixtech.com wrote:
> >> > From: Manikandan K Pillai <mpillai@cadence.com>
> >> >
> >> > Document the compatible property for HPA (High Performance
> >Architecture)
> >> > PCIe controller EP configuration.
> >>
> >> Please explain what makes the new architecture sufficiently different
> >> from the existing one such that a fallback compatible does not work.
> >>
> >> Same applies to the other binding patch.
> >
> >Additionally, since this IP is likely in use on your sky1 SoC, why is a
> >soc-specific compatible for your integration not needed?
> >
>
> The sky1 SoC support patches will be developed and submitted by the Sky1
> team separately.

Why? Cixtech sent this patchset, they should send it with their user.

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