Re: [PATCH v4 0/5] Enhance the PCIe controller driver

Krzysztof Kozlowski
2025-04-25T16:24:36Z

On 24/04/2025 03:04, hans.zhang@cixtech.com wrote:
> From: Hans Zhang <hans.zhang@cixtech.com>
>
> Enhances the exiting Cadence PCIe controller drivers to support
> HPA (High Performance Architecture) Cadence PCIe controllers.
>
> The patch set enhances the Cadence PCIe driver for HPA support.
> The "compatible" property in DTS is added with more enum to support
> the new platform architecture and the register maps that change with
> it. The driver read register and write register functions take the
> updated offset stored from the platform driver to access the registers.
> The driver now supports the legacy and HPA architecture, with the
> legacy code changes beingminimal.
>
> SoC related changes are not available in this patch set.
>
> The TI SoC continues to be supported with the changes incorporated.
>
> The changes are also in tune with how multiple platforms are supported
> in related drivers.
>
> The scripts/checkpatch.pl has been run on the patches with and without
> --strict. With the --strict option, 4 checks are generated on 1 patch
> (PATCH v3 3/6) of the series), which can be ignored. There are no code
> fixes required for these checks. The rest of the 'scripts/checkpatch.pl'
> is clean.
>
> The ./scripts/kernel-doc --none have been run on the changed files.
>
> The changes are tested on TI platforms. The legacy controller changes are
> tested on an TI J7200 EVM and HPA changes are planned for on an FPGA
> platform available within Cadence.
>
> Changes for v4
> - Add header file bitfield.h to pcie-cadence.h.
> - Addressed the following review comments.
> Merged the TI patch as it.
> Removed initialization of struct variables to '0'.

So the rest you did not address?

That's not acceptable. You ignored several comments such way. Either
discussion did not finish or you agree to implement all comments. If you
do not agree, then sending new version hides the previous discussion.
Best regards,
Krzysztof