Re: [PATCH v5 3/7] clocksource: stm32-lptimer: add support for stm32mp25

[kernel test robot <lkp@intel.com>]

Hi Fabrice,

kernel test robot noticed the following build warnings:

[auto build test WARNING on lee-mfd/for-mfd-next]
[also build test WARNING on lee-leds/for-leds-next linus/master v6.15-rc3 next-20250424]
[cannot apply to atorgue-stm32/stm32-next lee-mfd/for-mfd-fixes]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Fabrice-Gasnier/dt-bindings-mfd-stm32-lptimer-add-support-for-stm32mp25/20250425-210409
base:   https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git for-mfd-next
patch link:    https://lore.kernel.org/r/20250425124755.166193-4-fabrice.gasnier%40foss.st.com
patch subject: [PATCH v5 3/7] clocksource: stm32-lptimer: add support for stm32mp25
config: arm-randconfig-003-20250426 (https://download.01.org/0day-ci/archive/20250426/202504261456.aCATBoYN-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project f819f46284f2a79790038e1f6649172789734ae8)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250426/202504261456.aCATBoYN-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202504261456.aCATBoYN-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/clocksource/timer-stm32-lp.c:57:6: warning: logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses]
      57 |         if (!val & STM32_LPTIM_ENABLE) {
         |             ^    ~
   drivers/clocksource/timer-stm32-lp.c:57:6: note: add parentheses after the '!' to evaluate the bitwise operator first
      57 |         if (!val & STM32_LPTIM_ENABLE) {
         |             ^                        
         |              (                       )
   drivers/clocksource/timer-stm32-lp.c:57:6: note: add parentheses around left hand side expression to silence this warning
      57 |         if (!val & STM32_LPTIM_ENABLE) {
         |             ^
         |             (   )
   1 warning generated.


vim +57 drivers/clocksource/timer-stm32-lp.c

    50	
    51	static int stm32mp25_clkevent_lp_set_evt(struct stm32_lp_private *priv, unsigned long evt)
    52	{
    53		int ret;
    54		u32 val;
    55	
    56		regmap_read(priv->reg, STM32_LPTIM_CR, &val);
  > 57		if (!val & STM32_LPTIM_ENABLE) {
    58			/* Enable LPTIMER to be able to write into IER and ARR registers */
    59			regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE);
    60			/*
    61			 * After setting the ENABLE bit, a delay of two counter clock cycles is needed
    62			 * before the LPTIM is actually enabled. For 32KHz rate, this makes approximately
    63			 * 62.5 micro-seconds, round it up.
    64			 */
    65			udelay(63);
    66		}
    67		/* set next event counter */
    68		regmap_write(priv->reg, STM32_LPTIM_ARR, evt);
    69		/* enable ARR interrupt */
    70		regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE);
    71	
    72		/* Poll DIEROK and ARROK to ensure register access has completed */
    73		ret = regmap_read_poll_timeout_atomic(priv->reg, STM32_LPTIM_ISR, val,
    74						      (val & STM32_LPTIM_DIEROK_ARROK) ==
    75						      STM32_LPTIM_DIEROK_ARROK,
    76						      10, 500);
    77		if (ret) {
    78			dev_err(priv->dev, "access to LPTIM timed out\n");
    79			/* Disable LPTIMER */
    80			regmap_write(priv->reg, STM32_LPTIM_CR, 0);
    81			return ret;
    82		}
    83		/* Clear DIEROK and ARROK flags */
    84		regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_DIEROKCF_ARROKCF);
    85	
    86		return 0;
    87	}
    88	

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