From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36FDC185B48 for ; Sat, 3 May 2025 15:45:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746287144; cv=none; b=O8Lmv+yQW8CYK/FwITprsUL0Gjy3QyMShWTPDHb8BMlJZNQF8jecVReEoFXFXp+DQ3scZaQngFqDej1cj2aVmyjmWiy0P6fgf8u7N59R/GNVwG9KY245n50J5Ye8HBZduzHeAOBFi0qpaYqVCqN7wD9DKkCWtzvcqex6b6d2K1w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746287144; c=relaxed/simple; bh=EGigMOqKpMLne7DEzms28LfFgAq27NTDs9hZyHgLz/I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BED6ZQwPMGsp3pXRfs+6QExUs3k1V4eBj1B3RiaFnWxi01Bj/do37dCRIdvT+FFoXEKL3jG6tYqSadQf6vFxkuxFi6SSDjjCABIepFti3MLsiCgpfIDF1kau/DUbeuIJVDp/F5mUZQW5r5urb0s+6oON7A/vV96bHi2bWMYV+E4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 543FJg9e088156 for ; Sat, 3 May 2025 23:19:42 +0800 (+08) (envelope-from ben717@andestech.com) Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 543FIkLE087578 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 3 May 2025 23:18:46 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Sat, 3 May 2025 23:18:46 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , "Ben Zong-You Xie" Subject: [PATCH v2 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Date: Sat, 3 May 2025 23:18:24 +0800 Message-ID: <20250503151829.605006-5-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250503151829.605006-1-ben717@andestech.com> References: <20250503151829.605006-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 543FJg9e088156 Add the DT binding documentation for Andes machine-level software interrupt controller. In the Andes platform such as QiLai SoC, the PLIC module is instantiated a second time with all interrupt sources tied to zero as the software interrupt controller (PLICSW). PLICSW can generate machine-level software interrupts through programming its registers. Signed-off-by: Ben Zong-You Xie --- .../andestech,plicsw.yaml | 54 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml new file mode 100644 index 000000000000..eb2eb611ac09 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes machine-level software interrupt controller + +description: + In the Andes platform such as QiLai SoC, the PLIC module is instantiated a + second time with all interrupt sources tied to zero as the software interrupt + controller (PLIC_SW). PLIC_SW directly connects to the machine-mode + inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt + controller is the parent interrupt controller for PLIC_SW. PLIC_SW can + generate machine-mode inter-processor interrupts through programming its + registers. + +maintainers: + - Ben Zong-You Xie + +properties: + compatible: + items: + - enum: + - andestech,qilai-plicsw + - const: andestech,plicsw + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 15872 + description: + Specifies which harts are connected to the PLIC_SW. Each item must points + to a riscv,cpu-intc node, which has a riscv cpu node as parent. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@400000 { + compatible = "andestech,qilai-plicsw", "andestech,plicsw"; + reg = <0x400000 0x400000>; + interrupts-extended = <&cpu0intc 3>, + <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 8ac96b1f2e09..856753183687 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20812,6 +20812,7 @@ F: include/linux/irqchip/riscv-imsic.h RISC-V ANDES SoC Support M: Ben Zong-You Xie S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml F: Documentation/devicetree/bindings/riscv/andes.yaml RISC-V ARCHITECTURE -- 2.34.1