[PATCH 00/11] Add Tegra264 support

[PATCH 00/11] Add Tegra264 support

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Hi,

this series of patches adds some of the building blocks to enable
support for the new Tegra264 SoC. It's similar to earlier generations
but has some significant changes that need new compatible strings, so
this is mostly adding those differences.

This also includes a patch to fix an Kconfig dependency issue that can
happen.

Thierry

Thierry Reding (11):
  dt-bindings: tegra: pmc: Add Tegra264 compatible
  dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts
  dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list
  dt-bindings: firmware: Document Tegra264 BPMP
  dt-bindings: misc: Document Tegra264 APBMISC compatible
  soc/tegra: Enable support for Tegra264
  soc/tegra: pmc: Add Tegra264 support
  soc/tegra: Add Tegra264 APBMISC compatible string
  firmware: tegra: Fix IVC dependency problems
  firmware: tegra: bpmp: Add support on Tegra264
  arm64: defconfig: Enable Tegra HSP and BPMP

 .../arm/tegra/nvidia,tegra186-pmc.yaml        |   1 +
 .../firmware/nvidia,tegra186-bpmp.yaml        |   1 +
 .../bindings/mailbox/nvidia,tegra186-hsp.yaml |  23 ++-
 .../bindings/misc/nvidia,tegra186-misc.yaml   |   1 +
 arch/arm64/configs/defconfig                  |   2 +
 drivers/firmware/tegra/Kconfig                |   5 +-
 drivers/firmware/tegra/bpmp.c                 |   6 +-
 drivers/soc/tegra/Kconfig                     |  17 ++-
 drivers/soc/tegra/fuse/tegra-apbmisc.c        |   1 +
 drivers/soc/tegra/pmc.c                       | 132 +++++++++++++++++-
 10 files changed, 171 insertions(+), 18 deletions(-)

-- 
2.49.0

[PATCH 01/11] dt-bindings: tegra: pmc: Add Tegra264 compatible

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The PMC found on Tegra264 is similar to the version in earlier chips but
some of the register offsets and bitfields differ, so add a specific
compatible string for this new generation.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
index ea4fbf655220..be70819020c5 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
@@ -16,6 +16,7 @@ properties:
       - nvidia,tegra186-pmc
       - nvidia,tegra194-pmc
       - nvidia,tegra234-pmc
+      - nvidia,tegra264-pmc
 
   reg:
     minItems: 4
-- 
2.49.0

[PATCH 02/11] dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

It turns out that some instances of the HSP block on Tegra264 can have
up to 16 shared interrupts, so bump the maximum number of allowed
interrupts.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 21 ++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
index 2d14fc948999..df6784a7c96a 100644
--- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
@@ -76,7 +76,7 @@ properties:
 
   interrupts:
     minItems: 1
-    maxItems: 9
+    maxItems: 17
 
   interrupt-names:
     oneOf:
@@ -84,6 +84,25 @@ properties:
       - items:
           - const: doorbell
 
+      - items:
+          - const: doorbell
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+          - pattern: "^shared[1]?[0-9]$"
+
       - items:
           - const: doorbell
           - pattern: "^shared[0-7]$"
-- 
2.49.0

[PATCH 03/11] dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

We want these strings to be sorted in order of release date of the
chips, so the Tegra264 entry should go after the Tegra234 entry.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml        | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
index df6784a7c96a..cbc02b2a156a 100644
--- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
@@ -66,10 +66,10 @@ properties:
     oneOf:
       - const: nvidia,tegra186-hsp
       - const: nvidia,tegra194-hsp
-      - const: nvidia,tegra264-hsp
       - items:
           - const: nvidia,tegra234-hsp
           - const: nvidia,tegra194-hsp
+      - const: nvidia,tegra264-hsp
 
   reg:
     maxItems: 1
-- 
2.49.0

[PATCH 04/11] dt-bindings: firmware: Document Tegra264 BPMP

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

While the BPMP found on Tegra264 is similar to the versions found on
previous chips and should be backwards-compatible, some changes could
eventually be needed. Anticipate such changes and introduce a chip-
specific compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
index c43d17f6e96b..3c44fe607e12 100644
--- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
+++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
@@ -70,6 +70,7 @@ properties:
           - enum:
               - nvidia,tegra194-bpmp
               - nvidia,tegra234-bpmp
+              - nvidia,tegra264-bpmp
           - const: nvidia,tegra186-bpmp
       - const: nvidia,tegra186-bpmp
 
-- 
2.49.0

[PATCH 05/11] dt-bindings: misc: Document Tegra264 APBMISC compatible

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
index cacb845868f4..87fcce7cbb40 100644
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
@@ -20,6 +20,7 @@ properties:
       - nvidia,tegra186-misc
       - nvidia,tegra194-misc
       - nvidia,tegra234-misc
+      - nvidia,tegra264-misc
 
   reg:
     items:
-- 
2.49.0

[PATCH 06/11] soc/tegra: Enable support for Tegra264

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Tegra264 is the successor to Tegra234, with various improvements and new
hardware.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/soc/tegra/Kconfig | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index 33512558af9f..bc532cbe32e7 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -138,6 +138,14 @@ config ARCH_TEGRA_241_SOC
 	help
 	  Enable support for the NVIDIA Tegra241 SoC.
 
+config ARCH_TEGRA_264_SOC
+	bool "NVIDIA Tegra264 SoC"
+	depends on !CPU_BIG_ENDIAN
+	select MAILBOX
+	select SOC_TEGRA_PMC
+	help
+	  Enable support for the NVIDIA Tegra264 SoC.
+
 endif
 endif
 
-- 
2.49.0

[PATCH 07/11] soc/tegra: pmc: Add Tegra264 support

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The PMC block on Tegra264 has undergone a few small changes since it's
Tegra234 predecessor. Match on the new compatible string to select the
updated SoC-specific data.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/soc/tegra/pmc.c | 132 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 129 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 51b9d852bb6a..6f1ea5b6b9db 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -2892,9 +2892,14 @@ static int tegra_pmc_probe(struct platform_device *pdev)
 		if (IS_ERR(pmc->wake))
 			return PTR_ERR(pmc->wake);
 
-		pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag");
-		if (IS_ERR(pmc->aotag))
-			return PTR_ERR(pmc->aotag);
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
+		if (res) {
+			pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
+			if (IS_ERR(pmc->aotag))
+				return PTR_ERR(pmc->aotag);
+		} else {
+			pmc->aotag = NULL;
+		}
 
 		/* "scratch" is an optional aperture */
 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
@@ -4247,7 +4252,128 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = {
 	.has_single_mmio_aperture = false,
 };
 
+static const struct tegra_pmc_regs tegra264_pmc_regs = {
+	.scratch0 = 0x684,
+	.rst_status = 0x4,
+	.rst_source_shift = 0x2,
+	.rst_source_mask = 0x1fc,
+	.rst_level_shift = 0x0,
+	.rst_level_mask = 0x3,
+};
+
+static const char * const tegra264_reset_sources[] = {
+	"SYS_RESET_N",		/* 0x0 */
+	"CSDC_RTC_XTAL",
+	"VREFRO_POWER_BAD",
+	"SCPM_SOC_XTAL",
+	"SCPM_RTC_XTAL",
+	"FMON_32K",
+	"FMON_OSC",
+	"POD_RTC",
+	"POD_IO",		/* 0x8 */
+	"POD_PLUS_IO_SPLL",
+	"POD_PLUS_SOC",
+	"VMON_PLUS_UV",
+	"VMON_PLUS_OV",
+	"FUSECRC_FAULT",
+	"OSC_FAULT",
+	"BPMP_BOOT_FAULT",
+	"SCPM_BPMP_CORE_CLK",	/* 0x10 */
+	"SCPM_PSC_SE_CLK",
+	"VMON_SOC_MIN",
+	"VMON_SOC_MAX",
+	"VMON_MSS_MIN",
+	"VMON_MSS_MAX",
+	"POD_PLUS_IO_VMON",
+	"NVJTAG_SEL_MONITOR",
+	"NV_THERM_FAULT",	/* 0x18 */
+	"FSI_THERM_FAULT",
+	"PSC_SW",
+	"SCPM_OESP_SE_CLK",
+	"SCPM_SB_SE_CLK",
+	"POD_CPU",
+	"POD_GPU",
+	"DCLS_GPU",
+	"POD_MSS",		/* 0x20 */
+	"FMON_FSI",
+	"POD_FSI",
+	"VMON_FSI_MIN",
+	"VMON_FSI_MAX",
+	"VMON_CPU0_MIN",
+	"VMON_CPU0_MAX",
+	"BPMP_FMON",
+	"AO_WDT_POR",		/* 0x28 */
+	"BPMP_WDT_POR",
+	"AO_TKE_WDT_POR",
+	"RCE0_WDT_POR",
+	"RCE1_WDT_POR",
+	"DCE_WDT_POR",
+	"FSI_R5_WDT_POR",
+	"FSI_R52_0_WDT_POR",
+	"FSI_R52_1_WDT_POR",	/* 0x30 */
+	"FSI_R52_2_WDT_POR",
+	"FSI_R52_3_WDT_POR",
+	"TOP_0_WDT_POR",
+	"TOP_1_WDT_POR",
+	"TOP_2_WDT_POR",
+	"APE_C0_WDT_POR",
+	"APE_C1_WDT_POR",
+	"GPU_TKE_WDT_POR",	/* 0x38 */
+	"PSC_WDT_POR",
+	"OESP_WDT_POR",
+	"SB_WDT_POR",
+	"SW_MAIN",
+	"L0L1_RST_OUT_N",
+	"FSI_HSM",
+	"CSITE_SW",
+	"AO_WDT_DBG",		/* 0x40 */
+	"BPMP_WDT_DBG",
+	"AO_TKE_WDT_DBG",
+	"RCE0_WDT_DBG",
+	"RCE1_WDT_DBG",
+	"DCE_WDT_DBG",
+	"FSI_R5_WDT_DBG",
+	"FSI_R52_0_WDT_DBG",
+	"FSI_R52_1_WDT_DBG",	/* 0x48 */
+	"FSI_R52_2_WDT_DBG",
+	"FSI_R52_3_WDT_DBG",
+	"TOP_0_WDT_DBG",
+	"TOP_1_WDT_DBG",
+	"TOP_2_WDT_DBG",
+	"APE_C0_WDT_DBG",
+	"APE_C1_WDT_DBG",
+	"PSC_WDT_DBG",		/* 0x50 */
+	"OESP_WDT_DBG",
+	"SB_WDT_DBG",
+	"TSC_0_WDT_DBG",
+	"TSC_1_WDT_DBG",
+	"L2_RST_OUT_N",
+	"SC7"
+};
+
+static const struct tegra_wake_event tegra264_wake_events[] = {
+};
+
+static const struct tegra_pmc_soc tegra264_pmc_soc = {
+	.has_impl_33v_pwr = true,
+	.regs = &tegra264_pmc_regs,
+	.init = tegra186_pmc_init,
+	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
+	.set_wake_filters = tegra186_pmc_set_wake_filters,
+	.irq_set_wake = tegra186_pmc_irq_set_wake,
+	.irq_set_type = tegra186_pmc_irq_set_type,
+	.reset_sources = tegra264_reset_sources,
+	.num_reset_sources = ARRAY_SIZE(tegra264_reset_sources),
+	.reset_levels = tegra186_reset_levels,
+	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
+	.wake_events = tegra264_wake_events,
+	.num_wake_events = ARRAY_SIZE(tegra264_wake_events),
+	.max_wake_events = 128,
+	.max_wake_vectors = 4,
+};
+
 static const struct of_device_id tegra_pmc_match[] = {
+	{ .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc },
 	{ .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
 	{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
 	{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
-- 
2.49.0

[PATCH 08/11] soc/tegra: Add Tegra264 APBMISC compatible string

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/soc/tegra/fuse/tegra-apbmisc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
index e2ca5d55fd31..0ce94fdc536f 100644
--- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -128,6 +128,7 @@ static const struct of_device_id apbmisc_match[] __initconst = {
 	{ .compatible = "nvidia,tegra186-misc", },
 	{ .compatible = "nvidia,tegra194-misc", },
 	{ .compatible = "nvidia,tegra234-misc", },
+	{ .compatible = "nvidia,tegra264-misc", },
 	{},
 };
 
-- 
2.49.0

[PATCH 09/11] firmware: tegra: Fix IVC dependency problems

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The IVC code is library code that other drivers need to select if they
need that library. However, if the symbol is user-selectable this can
lead to conflicts.

Fix this by making the symbol only selectable for COMPILE_TEST and add
a select TEGRA_IVC to TEGRA_BPMP, which is currently the only user.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/firmware/tegra/Kconfig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/firmware/tegra/Kconfig b/drivers/firmware/tegra/Kconfig
index cde1ab8bd9d1..91f2320c0d0f 100644
--- a/drivers/firmware/tegra/Kconfig
+++ b/drivers/firmware/tegra/Kconfig
@@ -2,7 +2,7 @@
 menu "Tegra firmware driver"
 
 config TEGRA_IVC
-	bool "Tegra IVC protocol"
+	bool "Tegra IVC protocol" if COMPILE_TEST
 	depends on ARCH_TEGRA
 	help
 	  IVC (Inter-VM Communication) protocol is part of the IPC
@@ -13,8 +13,9 @@ config TEGRA_IVC
 
 config TEGRA_BPMP
 	bool "Tegra BPMP driver"
-	depends on ARCH_TEGRA && TEGRA_HSP_MBOX && TEGRA_IVC
+	depends on ARCH_TEGRA && TEGRA_HSP_MBOX
 	depends on !CPU_BIG_ENDIAN
+	select TEGRA_IVC
 	help
 	  BPMP (Boot and Power Management Processor) is designed to off-loading
 	  the PM functions which include clock/DVFS/thermal/power from the CPU.
-- 
2.49.0

[PATCH 10/11] firmware: tegra: bpmp: Add support on Tegra264

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Support for Tegra264 depends on the Tegra186 support, so make sure the
latter is enabled.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/firmware/tegra/bpmp.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c
index c3a1dc344961..e74bba7ccc44 100644
--- a/drivers/firmware/tegra/bpmp.c
+++ b/drivers/firmware/tegra/bpmp.c
@@ -836,7 +836,8 @@ static const struct dev_pm_ops tegra_bpmp_pm_ops = {
 
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
-    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
+    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
+    IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
 static const struct tegra_bpmp_soc tegra186_soc = {
 	.channels = {
 		.cpu_tx = {
@@ -884,7 +885,8 @@ static const struct tegra_bpmp_soc tegra210_soc = {
 static const struct of_device_id tegra_bpmp_match[] = {
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
-    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
+    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
+    IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
 	{ .compatible = "nvidia,tegra186-bpmp", .data = &tegra186_soc },
 #endif
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
-- 
2.49.0

[PATCH 11/11] arm64: defconfig: Enable Tegra HSP and BPMP

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Selecting the IVC, HSP and BPMP drivers via Kconfig is problematic
because it can create conflicting configurations. Instead, enable them
in the default configuration.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/configs/defconfig | 2 ++
 drivers/soc/tegra/Kconfig    | 9 ---------
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 98ad22833282..85582019be04 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -266,6 +266,7 @@ CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE=y
 CONFIG_QCOM_QSEECOM=y
 CONFIG_QCOM_QSEECOM_UEFISECAPP=y
 CONFIG_EXYNOS_ACPM_PROTOCOL=m
+CONFIG_TEGRA_BPMP=y
 CONFIG_GNSS=m
 CONFIG_GNSS_MTK_SERIAL=m
 CONFIG_MTD=y
@@ -1431,6 +1432,7 @@ CONFIG_PLATFORM_MHU=y
 CONFIG_BCM2835_MBOX=y
 CONFIG_QCOM_APCS_IPC=y
 CONFIG_MTK_ADSP_MBOX=m
+CONFIG_TEGRA_HSP_MBOX=y
 CONFIG_QCOM_IPCC=y
 CONFIG_ROCKCHIP_IOMMU=y
 CONFIG_TEGRA_IOMMU_SMMU=y
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index bc532cbe32e7..9392c2c43cc8 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -97,9 +97,6 @@ config ARCH_TEGRA_186_SOC
 	bool "NVIDIA Tegra186 SoC"
 	depends on !CPU_BIG_ENDIAN
 	select MAILBOX
-	select TEGRA_BPMP
-	select TEGRA_HSP_MBOX
-	select TEGRA_IVC
 	select SOC_TEGRA_PMC
 	help
 	  Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
@@ -114,9 +111,6 @@ config ARCH_TEGRA_194_SOC
 	depends on !CPU_BIG_ENDIAN
 	select MAILBOX
 	select PINCTRL_TEGRA194
-	select TEGRA_BPMP
-	select TEGRA_HSP_MBOX
-	select TEGRA_IVC
 	select SOC_TEGRA_PMC
 	help
 	  Enable support for the NVIDIA Tegra194 SoC.
@@ -126,9 +120,6 @@ config ARCH_TEGRA_234_SOC
 	depends on !CPU_BIG_ENDIAN
 	select MAILBOX
 	select PINCTRL_TEGRA234
-	select TEGRA_BPMP
-	select TEGRA_HSP_MBOX
-	select TEGRA_IVC
 	select SOC_TEGRA_PMC
 	help
 	  Enable support for the NVIDIA Tegra234 SoC.
-- 
2.49.0

Re: [PATCH 07/11] soc/tegra: pmc: Add Tegra264 support

[Jon Hunter]

On 06/05/2025 14:31, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The PMC block on Tegra264 has undergone a few small changes since it's
> Tegra234 predecessor. Match on the new compatible string to select the
> updated SoC-specific data.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/soc/tegra/pmc.c | 132 +++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 129 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index 51b9d852bb6a..6f1ea5b6b9db 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -2892,9 +2892,14 @@ static int tegra_pmc_probe(struct platform_device *pdev)
>   		if (IS_ERR(pmc->wake))
>   			return PTR_ERR(pmc->wake);
>   
> -		pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag");
> -		if (IS_ERR(pmc->aotag))
> -			return PTR_ERR(pmc->aotag);
> +		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
> +		if (res) {
> +			pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
> +			if (IS_ERR(pmc->aotag))
> +				return PTR_ERR(pmc->aotag);
> +		} else {
> +			pmc->aotag = NULL;
> +		}

This part make aotag optional, if I understand this correctly. This is 
not mentioned above and probably should be. Also, I believe that 
currently dt-binding has this as required and so we should update the 
dt-binding doc to make this optional too.

Jon

-- 
nvpublic

Re: [PATCH 07/11] soc/tegra: pmc: Add Tegra264 support

[Thierry Reding]

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On Wed, May 07, 2025 at 12:03:39PM +0100, Jon Hunter wrote:
> 
> On 06/05/2025 14:31, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > The PMC block on Tegra264 has undergone a few small changes since it's
> > Tegra234 predecessor. Match on the new compatible string to select the
> > updated SoC-specific data.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >   drivers/soc/tegra/pmc.c | 132 +++++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 129 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> > index 51b9d852bb6a..6f1ea5b6b9db 100644
> > --- a/drivers/soc/tegra/pmc.c
> > +++ b/drivers/soc/tegra/pmc.c
> > @@ -2892,9 +2892,14 @@ static int tegra_pmc_probe(struct platform_device *pdev)
> >   		if (IS_ERR(pmc->wake))
> >   			return PTR_ERR(pmc->wake);
> > -		pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag");
> > -		if (IS_ERR(pmc->aotag))
> > -			return PTR_ERR(pmc->aotag);
> > +		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
> > +		if (res) {
> > +			pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
> > +			if (IS_ERR(pmc->aotag))
> > +				return PTR_ERR(pmc->aotag);
> > +		} else {
> > +			pmc->aotag = NULL;
> > +		}
> 
> This part make aotag optional, if I understand this correctly. This is not
> mentioned above and probably should be. Also, I believe that currently
> dt-binding has this as required and so we should update the dt-binding doc
> to make this optional too.

Good catch. I actually noticed earlier, as I was going over the next set
of patches once more, that there's actually an AOTAG region in the PMC's
address space, so I'm leaning towards dropping the above hunk and leave
the DT bindings as they are.

When it comes to these AOTAG registers, it's a bit difficult to tell
because we don't ever use them after mapping them, even on older Tegra
generations. Keeping it for now should be fine, and we can subsequently
drop them (and the driver could always just continue ignoring them) if
there's a good reason.

Thierry

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Re: [PATCH 01/11] dt-bindings: tegra: pmc: Add Tegra264 compatible

[Rob Herring (Arm)]

On Tue, 06 May 2025 15:31:08 +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The PMC found on Tegra264 is similar to the version in earlier chips but
> some of the register offsets and bitfields differ, so add a specific
> compatible string for this new generation.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml       | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 02/11] dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts

[Rob Herring]

On Tue, May 06, 2025 at 03:31:09PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> It turns out that some instances of the HSP block on Tegra264 can have
> up to 16 shared interrupts, so bump the maximum number of allowed
> interrupts.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 21 ++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> index 2d14fc948999..df6784a7c96a 100644
> --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> @@ -76,7 +76,7 @@ properties:
>  
>    interrupts:
>      minItems: 1
> -    maxItems: 9
> +    maxItems: 17
>  
>    interrupt-names:
>      oneOf:
> @@ -84,6 +84,25 @@ properties:
>        - items:
>            - const: doorbell
>  
> +      - items:
> +          - const: doorbell
> +          - pattern: "^shared[1]?[0-9]$"

shared1?[0-9] works

Though really it should be: "^shared([0-9]|1[0-5])$"

With that,

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +          - pattern: "^shared[1]?[0-9]$"
> +
>        - items:
>            - const: doorbell
>            - pattern: "^shared[0-7]$"
> -- 
> 2.49.0
> 

Re: [PATCH 03/11] dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list

[Rob Herring]

On Tue, May 06, 2025 at 03:31:10PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> We want these strings to be sorted in order of release date of the
> chips, so the Tegra264 entry should go after the Tegra234 entry.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml        | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> index df6784a7c96a..cbc02b2a156a 100644
> --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> @@ -66,10 +66,10 @@ properties:
>      oneOf:
>        - const: nvidia,tegra186-hsp
>        - const: nvidia,tegra194-hsp
> -      - const: nvidia,tegra264-hsp
>        - items:
>            - const: nvidia,tegra234-hsp
>            - const: nvidia,tegra194-hsp
> +      - const: nvidia,tegra264-hsp

The preference here is really to put all the single entry cases into 1 
enum. Order by release would be okay, but not something the DT 
maintainers know or can remember which bindings do that. So alphanumeric 
order is preferred.

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Rob

Re: [PATCH 04/11] dt-bindings: firmware: Document Tegra264 BPMP

[Rob Herring (Arm)]

On Tue, 06 May 2025 15:31:11 +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> While the BPMP found on Tegra264 is similar to the versions found on
> previous chips and should be backwards-compatible, some changes could
> eventually be needed. Anticipate such changes and introduce a chip-
> specific compatible string.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml       | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 05/11] dt-bindings: misc: Document Tegra264 APBMISC compatible

[Rob Herring (Arm)]

On Tue, 06 May 2025 15:31:12 +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 01/11] dt-bindings: tegra: pmc: Add Tegra264 compatible

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>


On Tue, 06 May 2025 15:31:08 +0200, Thierry Reding wrote:
> The PMC found on Tegra264 is similar to the version in earlier chips but
> some of the register offsets and bitfields differ, so add a specific
> compatible string for this new generation.
> 
> 

Applied, thanks!

[01/11] dt-bindings: tegra: pmc: Add Tegra264 compatible
        commit: 5b820eb176846dad95b0a45dcfe788931f5e7527

Best regards,
-- 
Thierry Reding <treding@nvidia.com>

Re: [PATCH 02/11] dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>


On Tue, 06 May 2025 15:31:09 +0200, Thierry Reding wrote:
> It turns out that some instances of the HSP block on Tegra264 can have
> up to 16 shared interrupts, so bump the maximum number of allowed
> interrupts.
> 
> 

Applied, thanks!

[02/11] dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts
        commit: b6be35ae29a38431e554d3ad35ec552058058ae6

Best regards,
-- 
Thierry Reding <treding@nvidia.com>