[net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS

devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed

* [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS
@ 2025-05-10 10:23 Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 01/11] net: phylink: keep and use MAC supported_interfaces in phylink struct Christian Marangi
                   ` (10 more replies)
  0 siblings, 11 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

This series introduce a most awaited feature that is correctly
provide PCS with fwnode without having to use specific export symbol
and additional handling of PCS in phylink.

There is currently an equivalent series for this feature where
a wrapper implementation is proposed. I honestly don't really like
introducing layer of layer of wrapping to workaround stuff, so
this is my attempt at giving a more direct approach to this.

---
First the PCS fwnode:

The concept is to implement a producer-consumer API similar to other
subsystem like clock or PHY.

That seems to be the best solution to the problem as PCS driver needs
to be detached from phylink and implement a simple way to provide a
PCS while maintaining support for probe defer or driver removal.

To keep the implementation simple, the PCS driver devs needs some
collaboration to correctly implement this. This is O.K. as helper
to correctly implement this are provided hence it's really a matter
of following a pattern to correct follow removal of a PCS driver.

A PCS provider have to implement and call fwnode_pcs_add_provider() in
probe function and define an xlate function to define how the PCS
should be provided based on the requested interface and phandle spec
defined in fwnode (based on the #pcs-cells)

fwnode_pcs_get() is provided to provide a specific PCS declared in
fwnode at index.

A simple xlate function is provided for simple single PCS
implementation, fwnode_pcs_simple_get.

A PCS provider on driver removal should first call
fwnode_pcs_del_provider() to delete itself as a provider and then
release the PCS from phylink with phylink_release_pcs() under rtnl
lock.

---
Second PCS handling in phylink:

We have the PCS problem for the only reason that in initial
implementation, we permitted way too much flexibility to MAC driver
and things started to deviate. At times we couldn't think SoC
would start to put PCS outside the MAC hence it was OK to assume
they would live in the same driver. With the introduction of
10g in more consumer devices, we are observing a rapid growth
of this pattern with multiple PCS external to MAC.

To put a stop on this, the only solution is to give back to phylink
control on PCS handling and enforce more robust supported interface
definition from both MAC and PCS side.

It's suggested to read patch 0003 of this series for more info, here
a brief explaination of the idea:

This series introduce handling of PCS in phylink and try to deprecate
.mac_select_pcs.

Phylink now might contain a linked list of available PCS and
those will be used for PCS selection on phylink_major_config.

MAC driver needs to define pcs_interfaces mask in phylink_config
for every interface that needs a dedicated PCS.

These PCS needs to be provided to phylink at phylink_create time
by setting the available_pcs and num_available_pcs in phylink_config.
A helper to parse PCS from fwnode is provided
fwnode_phylink_pcs_parse() that will fill a preallocated array of
PCS. (the same function can be used to get the number of PCS
defined in DT, more info in patch 0005)

phylink_create() will fill the internal PCS list with the passed
array of PCS. phylink_major_config and other user of .mac_select_pcs
are adapted to make use of this new PCS list.

The supported interface value is also moved internally to phylink
struct. This is to handle late removal and addition of PCS.
(the bonus effect to this is giving phylink a clear idea of what
is actually supported by the MAC and his constraint with PCS)

The supported interface mask in phylink is done by OR the
supported_interfaces in phylink_config with every PCS in PCS list.

PCS removal is supported by forcing a mac_config, refresh the
supported interfaces and run a phy_resolve().

PCS late addition is supported by introducing a global notifier
for PCS provider. If a phylink have the pcs_interfaces mask not
zero, it's registered to this notifier.

PCS provider will emit a global PCS add event to signal any
interface that a new PCS might be avialable.

The function will then check if the PCS is related to the MAC
fwnode and add it accordingly.

A user for this new implementation is provided as an Airoha PCS
driver. This was also tested downstream with the IPQ95xx QCOM SoC
and with the help of Daniel also on the various Mediatek MT7988
SoC with both SFP cage implementation and DSA attached.

Lots of tests were done with driver unbind/bind and with interface
up/down also by adding print to make sure major_config_fail gets
correctly triggered and reset once the PCS comes back.

The dedicated commits have longer description on the implementation
so it's suggested to also check there for additional info.

---

Changes v3:
- Out of RFC
- Fix various spelling mistake
- Drop circular dependency patch
- Complete Airoha Ethernet phylink integration
- Introduce .pcs_link_down PCS OP
Changes v2:
- Switch to fwnode
- Implement PCS provider notifier
- Better split changes
- Move supported_interfaces to phylink
- Add circular dependency patch
- Rework handling with indirect addition/removal and
  trigger of phylink_resolve()

Christian Marangi (11):
  net: phylink: keep and use MAC supported_interfaces in phylink struct
  net: phy: introduce phy_interface_copy helper
  net: phylink: introduce internal phylink PCS handling
  net: phylink: add phylink_release_pcs() to externally release a PCS
  net: pcs: implement Firmware node support for PCS driver
  net: phylink: support late PCS provider attach
  dt-bindings: net: ethernet-controller: permit to define multiple PCS
  net: phylink: add .pcs_link_down PCS OP
  net: pcs: airoha: add PCS driver for Airoha SoC
  dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
  net: airoha: add phylink support for GDM2/3/4

 .../bindings/net/ethernet-controller.yaml     |    2 -
 .../bindings/net/pcs/airoha,pcs.yaml          |  112 +
 drivers/net/ethernet/airoha/airoha_eth.c      |  138 +
 drivers/net/ethernet/airoha/airoha_eth.h      |    3 +
 drivers/net/ethernet/airoha/airoha_regs.h     |   12 +
 drivers/net/pcs/Kconfig                       |   14 +
 drivers/net/pcs/Makefile                      |    2 +
 drivers/net/pcs/core.c                        |  241 ++
 drivers/net/pcs/pcs-airoha.c                  | 2920 +++++++++++++++++
 drivers/net/phy/phylink.c                     |  287 +-
 include/linux/pcs/pcs-provider.h              |   41 +
 include/linux/pcs/pcs.h                       |  104 +
 include/linux/phy.h                           |    5 +
 include/linux/phylink.h                       |   14 +
 14 files changed, 3867 insertions(+), 28 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
 create mode 100644 drivers/net/pcs/core.c
 create mode 100644 drivers/net/pcs/pcs-airoha.c
 create mode 100644 include/linux/pcs/pcs-provider.h
 create mode 100644 include/linux/pcs/pcs.h

-- 
2.48.1

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 01/11] net: phylink: keep and use MAC supported_interfaces in phylink struct
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 02/11] net: phy: introduce phy_interface_copy helper Christian Marangi
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Add in phylink struct a copy of supported_interfaces from phylink_config
and make use of that instead of relying on phylink_config value.

This in preparation for support of PCS handling internally to phylink
where a PCS can be removed or added after the phylink is created and we
need both a reference of the supported_interfaces value from
phylink_config and an internal value that can be updated with the new
PCS info.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/phy/phylink.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 0faa3d97e06b..ec42fd278604 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -59,6 +59,11 @@ struct phylink {
 	/* The link configuration settings */
 	struct phylink_link_state link_config;
 
+	/* What interface are supported by the current link.
+	 * Can change on removal or addition of new PCS.
+	 */
+	DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+
 	/* The current settings */
 	phy_interface_t cur_interface;
 
@@ -610,7 +615,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
 static int phylink_validate(struct phylink *pl, unsigned long *supported,
 			    struct phylink_link_state *state)
 {
-	const unsigned long *interfaces = pl->config->supported_interfaces;
+	const unsigned long *interfaces = pl->supported_interfaces;
 
 	if (state->interface == PHY_INTERFACE_MODE_NA)
 		return phylink_validate_mask(pl, NULL, supported, state,
@@ -1809,6 +1814,9 @@ struct phylink *phylink_create(struct phylink_config *config,
 	mutex_init(&pl->state_mutex);
 	INIT_WORK(&pl->resolve, phylink_resolve);
 
+	phy_interface_copy(pl->supported_interfaces,
+			   config->supported_interfaces);
+
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
 		pl->netdev = to_net_dev(config->dev);
@@ -1967,7 +1975,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
 		 * those which the host supports.
 		 */
 		phy_interface_and(interfaces, phy->possible_interfaces,
-				  pl->config->supported_interfaces);
+				  pl->supported_interfaces);
 
 		if (phy_interface_empty(interfaces)) {
 			phylink_err(pl, "PHY has no common interfaces\n");
@@ -2684,12 +2692,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,
 		return interface;
 	}
 
-	if (!test_bit(interface, pl->config->supported_interfaces)) {
+	if (!test_bit(interface, pl->supported_interfaces)) {
 		phylink_err(pl,
 			    "selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\n",
 			    phy_modes(interface), interface,
 			    (int)PHY_INTERFACE_MODE_MAX,
-			    pl->config->supported_interfaces);
+			    pl->supported_interfaces);
 		return PHY_INTERFACE_MODE_NA;
 	}
 
@@ -3576,14 +3584,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)
 
 	phylink_dbg(pl, "optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\n",
 		    (int)PHY_INTERFACE_MODE_MAX,
-		    pl->config->supported_interfaces,
+		    pl->supported_interfaces,
 		    (int)PHY_INTERFACE_MODE_MAX,
 		    pl->sfp_interfaces);
 
 	/* Find the union of the supported interfaces by the PCS/MAC and
 	 * the SFP module.
 	 */
-	phy_interface_and(interfaces, pl->config->supported_interfaces,
+	phy_interface_and(interfaces, pl->supported_interfaces,
 			  pl->sfp_interfaces);
 	if (phy_interface_empty(interfaces)) {
 		phylink_err(pl, "unsupported SFP module: no common interface modes\n");
@@ -3729,7 +3737,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
 
 	/* Set the PHY's host supported interfaces */
 	phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
-			  pl->config->supported_interfaces);
+			  pl->supported_interfaces);
 
 	/* Do the initial configuration */
 	return phylink_sfp_config_phy(pl, phy);
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 02/11] net: phy: introduce phy_interface_copy helper
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 01/11] net: phylink: keep and use MAC supported_interfaces in phylink struct Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 03/11] net: phylink: introduce internal phylink PCS handling Christian Marangi
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Introduce phy_interface_copy helper as a shorthand to copy the PHY
interface bitmap to a different location.

This is useful if a PHY interface bitmap needs to be stored in a
different variable and needs to be reset to an original value saved in a
different bitmap.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 include/linux/phy.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/linux/phy.h b/include/linux/phy.h
index d62d292024bc..9f0e5fb30d63 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -173,6 +173,11 @@ static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
 	bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX);
 }
 
+static inline void phy_interface_copy(unsigned long *dst, const unsigned long *src)
+{
+	bitmap_copy(dst, src, PHY_INTERFACE_MODE_MAX);
+}
+
 static inline void phy_interface_set_rgmii(unsigned long *intf)
 {
 	__set_bit(PHY_INTERFACE_MODE_RGMII, intf);
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 03/11] net: phylink: introduce internal phylink PCS handling
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 01/11] net: phylink: keep and use MAC supported_interfaces in phylink struct Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 02/11] net: phy: introduce phy_interface_copy helper Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 04/11] net: phylink: add phylink_release_pcs() to externally release a PCS Christian Marangi
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Introduce internal handling of PCS for phylink. This is an alternative
to .mac_select_pcs that moves the selection logic of the PCS entirely to
phylink with the usage of the supported_interface value in the PCS
struct.

MAC should now provide an array of available PCS in phylink_config in
.available_pcs and fill the .num_available_pcs with the number of
elements in the array. MAC should also define a new bitmap,
pcs_interfaces, in phylink_config to define for what interface mode a
dedicated PCS is required.

On phylink_create() this array is parsed and a linked list of PCS is
created based on the PCS passed in phylink_config.
Also the supported_interface value in phylink struct is updated with the
new supported_interface from the provided PCS.

On phylink_start() every PCS in phylink PCS list gets attached to the
phylink instance. This is done by setting the phylink value in
phylink_pcs struct to the phylink instance.

On phylink_stop(), every PCS in phylink PCS list is detached from the
phylink instance. This is done by setting the phylink value in
phylink_pcs struct to NULL.

phylink_validate_mac_and_pcs(), phylink_major_config() and
phylink_inband_caps() are updated to support this new implementation
with the PCS list stored in phylink.

They will make use of phylink_validate_pcs_interface() that will loop
for every PCS in the phylink PCS available list and find one that supports
the passed interface.

phylink_validate_pcs_interface() applies the same logic of .mac_select_pcs
where if a supported_interface value is not set for the PCS struct, then
it's assumed every interface is supported.

A MAC is required to implement either a .mac_select_pcs or make use of
the PCS list implementation. Implementing both will result in a fail
on MAC/PCS validation.

phylink value in phylink_pcs struct with this implementation is used to
track from PCS side when it's attached to a phylink instance. PCS driver
will make use of this information to correctly detach from a phylink
instance if needed.

The .mac_select_pcs implementation is not changed but it's expected that
every MAC driver migrates to the new implementation to later deprecate
and remove .mac_select_pcs.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/phy/phylink.c | 147 +++++++++++++++++++++++++++++++++-----
 include/linux/phylink.h   |  10 +++
 2 files changed, 139 insertions(+), 18 deletions(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index ec42fd278604..95d7e06dee56 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -59,6 +59,9 @@ struct phylink {
 	/* The link configuration settings */
 	struct phylink_link_state link_config;
 
+	/* List of available PCS */
+	struct list_head pcs_list;
+
 	/* What interface are supported by the current link.
 	 * Can change on removal or addition of new PCS.
 	 */
@@ -144,6 +147,8 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {
 
 static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
 
+static void phylink_run_resolve(struct phylink *pl);
+
 /**
  * phylink_set_port_modes() - set the port type modes in the ethtool mask
  * @mask: ethtool link mode mask
@@ -499,22 +504,59 @@ static void phylink_validate_mask_caps(unsigned long *supported,
 	linkmode_and(state->advertising, state->advertising, mask);
 }
 
+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
+					  phy_interface_t interface)
+{
+	/* If PCS define an empty supported_interfaces value, assume
+	 * all interface are supported.
+	 */
+	if (phy_interface_empty(pcs->supported_interfaces))
+		return 0;
+
+	/* Ensure that this PCS supports the interface mode */
+	if (!test_bit(interface, pcs->supported_interfaces))
+		return -EINVAL;
+
+	return 0;
+}
+
 static int phylink_validate_mac_and_pcs(struct phylink *pl,
 					unsigned long *supported,
 					struct phylink_link_state *state)
 {
-	struct phylink_pcs *pcs = NULL;
 	unsigned long capabilities;
+	struct phylink_pcs *pcs;
+	bool pcs_found = false;
 	int ret;
 
 	/* Get the PCS for this interface mode */
 	if (pl->mac_ops->mac_select_pcs) {
+		/* Make sure either PCS internal validation or .mac_select_pcs
+		 * is used. Return error if both are defined.
+		 */
+		if (!list_empty(&pl->pcs_list)) {
+			phylink_err(pl, "either phylink_pcs_add() or .mac_select_pcs must be used\n");
+			return -EINVAL;
+		}
+
 		pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
 		if (IS_ERR(pcs))
 			return PTR_ERR(pcs);
+
+		pcs_found = !!pcs;
+	} else {
+		/* Check every assigned PCS and search for one that supports
+		 * the interface.
+		 */
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs, state->interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
 	}
 
-	if (pcs) {
+	if (pcs_found) {
 		/* The PCS, if present, must be setup before phylink_create()
 		 * has been called. If the ops is not initialised, print an
 		 * error and backtrace rather than oopsing the kernel.
@@ -526,13 +568,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
 			return -EINVAL;
 		}
 
-		/* Ensure that this PCS supports the interface which the MAC
-		 * returned it for. It is an error for the MAC to return a PCS
-		 * that does not support the interface mode.
-		 */
-		if (!phy_interface_empty(pcs->supported_interfaces) &&
-		    !test_bit(state->interface, pcs->supported_interfaces)) {
-			phylink_err(pl, "MAC returned PCS which does not support %s\n",
+		/* Recheck PCS to handle legacy way for .mac_select_pcs */
+		ret = phylink_validate_pcs_interface(pcs, state->interface);
+		if (ret) {
+			phylink_err(pl, "selected PCS does not support %s\n",
 				    phy_modes(state->interface));
 			return -EINVAL;
 		}
@@ -937,12 +976,22 @@ static unsigned int phylink_inband_caps(struct phylink *pl,
 					 phy_interface_t interface)
 {
 	struct phylink_pcs *pcs;
+	bool pcs_found = false;
 
-	if (!pl->mac_ops->mac_select_pcs)
-		return 0;
+	if (pl->mac_ops->mac_select_pcs) {
+		pcs = pl->mac_ops->mac_select_pcs(pl->config,
+						  interface);
+		pcs_found = !!pcs;
+	} else {
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs, interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
+	}
 
-	pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
-	if (!pcs)
+	if (!pcs_found)
 		return 0;
 
 	return phylink_pcs_inband_caps(pcs, interface);
@@ -1228,10 +1277,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
 			pl->major_config_failed = true;
 			return;
 		}
+	/* Find a PCS in available PCS list for the requested interface.
+	 * This doesn't overwrite the previous .mac_select_pcs as either
+	 * .mac_select_pcs or PCS list implementation are permitted.
+	 *
+	 * Skip searching if the MAC doesn't require a dedicaed PCS for
+	 * the requested interface.
+	 */
+	} else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+		bool pcs_found = false;
+
+		list_for_each_entry(pcs, &pl->pcs_list, list) {
+			if (!phylink_validate_pcs_interface(pcs,
+							    state->interface)) {
+				pcs_found = true;
+				break;
+			}
+		}
+
+		if (!pcs_found) {
+			phylink_err(pl,
+				    "couldn't find a PCS for %s\n",
+				    phy_modes(state->interface));
 
-		pcs_changed = pl->pcs != pcs;
+			pl->major_config_failed = true;
+			return;
+		}
 	}
 
+	pcs_changed = pl->pcs != pcs;
+
 	phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
 
 	phylink_dbg(pl, "major config, active %s/%s/%s\n",
@@ -1258,10 +1333,12 @@ static void phylink_major_config(struct phylink *pl, bool restart,
 	if (pcs_changed) {
 		phylink_pcs_disable(pl->pcs);
 
-		if (pl->pcs)
-			pl->pcs->phylink = NULL;
+		if (pl->mac_ops->mac_select_pcs) {
+			if (pl->pcs)
+				pl->pcs->phylink = NULL;
 
-		pcs->phylink = pl;
+			pcs->phylink = pl;
+		}
 
 		pl->pcs = pcs;
 	}
@@ -1797,8 +1874,9 @@ struct phylink *phylink_create(struct phylink_config *config,
 			       phy_interface_t iface,
 			       const struct phylink_mac_ops *mac_ops)
 {
+	struct phylink_pcs *pcs;
 	struct phylink *pl;
-	int ret;
+	int i, ret;
 
 	/* Validate the supplied configuration */
 	if (phy_interface_empty(config->supported_interfaces)) {
@@ -1813,9 +1891,21 @@ struct phylink *phylink_create(struct phylink_config *config,
 
 	mutex_init(&pl->state_mutex);
 	INIT_WORK(&pl->resolve, phylink_resolve);
+	INIT_LIST_HEAD(&pl->pcs_list);
+
+	/* Fill the PCS list with available PCS from phylink config */
+	for (i = 0; i < config->num_available_pcs; i++) {
+		pcs = config->available_pcs[i];
+
+		list_add(&pcs->list, &pl->pcs_list);
+	}
 
 	phy_interface_copy(pl->supported_interfaces,
 			   config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
 
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
@@ -1894,10 +1984,16 @@ EXPORT_SYMBOL_GPL(phylink_create);
  */
 void phylink_destroy(struct phylink *pl)
 {
+	struct phylink_pcs *pcs, *tmp;
+
 	sfp_bus_del_upstream(pl->sfp_bus);
 	if (pl->link_gpio)
 		gpiod_put(pl->link_gpio);
 
+	/* Remove every PCS from phylink PCS list */
+	list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list)
+		list_del(&pcs->list);
+
 	cancel_work_sync(&pl->resolve);
 	kfree(pl);
 }
@@ -2374,6 +2470,7 @@ static irqreturn_t phylink_link_handler(int irq, void *data)
  */
 void phylink_start(struct phylink *pl)
 {
+	struct phylink_pcs *pcs;
 	bool poll = false;
 
 	ASSERT_RTNL();
@@ -2400,6 +2497,10 @@ void phylink_start(struct phylink *pl)
 
 	pl->pcs_state = PCS_STATE_STARTED;
 
+	/* link available PCS to phylink struct */
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		pcs->phylink = pl;
+
 	phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED);
 
 	if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
@@ -2444,6 +2545,8 @@ EXPORT_SYMBOL_GPL(phylink_start);
  */
 void phylink_stop(struct phylink *pl)
 {
+	struct phylink_pcs *pcs;
+
 	ASSERT_RTNL();
 
 	if (pl->sfp_bus)
@@ -2461,6 +2564,14 @@ void phylink_stop(struct phylink *pl)
 	pl->pcs_state = PCS_STATE_DOWN;
 
 	phylink_pcs_disable(pl->pcs);
+
+	/* Drop link between phylink and PCS */
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		pcs->phylink = NULL;
+
+	/* Restore original supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
 }
 EXPORT_SYMBOL_GPL(phylink_stop);
 
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 30659b615fca..ef0b5a0729c8 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -150,12 +150,16 @@ enum phylink_op_type {
  *		     if MAC link is at %MLO_AN_FIXED mode.
  * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
  *                        are supported by the MAC/PCS.
+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
+ *		    dedicated PCS is required.
  * @lpi_interfaces: bitmap describing which PHY interface modes can support
  *		    LPI signalling.
  * @mac_capabilities: MAC pause/speed/duplex capabilities.
  * @lpi_capabilities: MAC speeds which can support LPI signalling
  * @lpi_timer_default: Default EEE LPI timer setting.
  * @eee_enabled_default: If set, EEE will be enabled by phylink at creation time
+ * @available_pcs: array of available phylink_pcs PCS
+ * @num_available_pcs: num of available phylink_pcs PCS
  */
 struct phylink_config {
 	struct device *dev;
@@ -168,11 +172,14 @@ struct phylink_config {
 	void (*get_fixed_state)(struct phylink_config *config,
 				struct phylink_link_state *state);
 	DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+	DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
 	DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
 	unsigned long mac_capabilities;
 	unsigned long lpi_capabilities;
 	u32 lpi_timer_default;
 	bool eee_enabled_default;
+	struct phylink_pcs **available_pcs;
+	unsigned int num_available_pcs;
 };
 
 void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
@@ -469,6 +476,9 @@ struct phylink_pcs {
 	struct phylink *phylink;
 	bool poll;
 	bool rxc_always_on;
+
+	/* private: */
+	struct list_head list;
 };
 
 /**
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 04/11] net: phylink: add phylink_release_pcs() to externally release a PCS
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
                   ` (2 preceding siblings ...)
  2025-05-10 10:23 ` [net-next PATCH v3 03/11] net: phylink: introduce internal phylink PCS handling Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 05/11] net: pcs: implement Firmware node support for PCS driver Christian Marangi
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Add phylink_release_pcs() to externally release a PCS from a phylink
instance. This can be used to handle case when a single PCS needs to be
removed and the phylink instance needs to be refreshed.

On calling phylink_release_pcs(), the PCS will be removed from the
phylink internal PCS list and the phylink supported_interfaces value is
reparsed with the remaining PCS interfaces.

Also a phylink resolve is triggered to handle the PCS removal.

A flag to make phylink resolve reconfigure the interface (even if it
didn't change) is also added. This is needed to handle the special
case when the current PCS used by phylink is removed and a major_config
is needed to propagae the configuration change. With this option
enabled we also force mac_config even if the PHY link is not up for
the in-band case.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/phy/phylink.c | 58 ++++++++++++++++++++++++++++++++++++++-
 include/linux/phylink.h   |  2 ++
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 95d7e06dee56..2f28c4c83062 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -84,6 +84,7 @@ struct phylink {
 	bool link_failed;
 	bool suspend_link_up;
 	bool major_config_failed;
+	bool reconfig_interface;
 	bool mac_supports_eee_ops;
 	bool mac_supports_eee;
 	bool phy_enable_tx_lpi;
@@ -895,6 +896,55 @@ static void phylink_resolve_an_pause(struct phylink_link_state *state)
 	}
 }
 
+/**
+ * phylink_release_pcs - Removes a PCS from the phylink PCS available list
+ * @pcs: a pointer to the phylink_pcs struct to be released
+ *
+ * This function release a PCS from the phylink PCS available list if
+ * actually in use. It also refreshes the supported interfaces of the
+ * phylink instance by copying the supported interfaces from the phylink
+ * conf and merging the supported interfaces of the remaining available PCS
+ * in the list and trigger a resolve.
+ */
+void phylink_release_pcs(struct phylink_pcs *pcs)
+{
+	struct phylink *pl;
+
+	ASSERT_RTNL();
+
+	pl = pcs->phylink;
+	if (!pl)
+		return;
+
+	list_del(&pcs->list);
+	pcs->phylink = NULL;
+
+	/* Check if we are removing the PCS currently
+	 * in use by phylink. If this is the case,
+	 * force phylink resolve to reconfigure the interface
+	 * mode and set the phylink PCS to NULL.
+	 */
+	if (pl->pcs == pcs) {
+		mutex_lock(&pl->state_mutex);
+
+		pl->reconfig_interface = true;
+		pl->pcs = NULL;
+
+		mutex_unlock(&pl->state_mutex);
+	}
+
+	/* Refresh supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
+
+	phylink_run_resolve(pl);
+}
+EXPORT_SYMBOL_GPL(phylink_release_pcs);
+
 static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs,
 				    phy_interface_t interface)
 {
@@ -1688,6 +1738,10 @@ static void phylink_resolve(struct work_struct *w)
 		if (pl->phydev)
 			link_state.link &= pl->phy_state.link;
 
+		/* Force mac_config if we need to reconfig the interface */
+		if (pl->reconfig_interface)
+			mac_config = true;
+
 		/* Only update if the PHY link is up */
 		if (pl->phydev && pl->phy_state.link) {
 			/* If the interface has changed, force a link down
@@ -1722,7 +1776,8 @@ static void phylink_resolve(struct work_struct *w)
 		phylink_apply_manual_flow(pl, &link_state);
 
 	if (mac_config) {
-		if (link_state.interface != pl->link_config.interface) {
+		if (link_state.interface != pl->link_config.interface ||
+		    pl->reconfig_interface) {
 			/* The interface has changed, force the link down and
 			 * then reconfigure.
 			 */
@@ -1732,6 +1787,7 @@ static void phylink_resolve(struct work_struct *w)
 			}
 			phylink_major_config(pl, false, &link_state);
 			pl->link_config.interface = link_state.interface;
+			pl->reconfig_interface = false;
 		}
 	}
 
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index ef0b5a0729c8..c5496c063b6a 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -717,6 +717,8 @@ void phylink_disconnect_phy(struct phylink *);
 int phylink_set_fixed_link(struct phylink *,
 			   const struct phylink_link_state *);
 
+void phylink_release_pcs(struct phylink_pcs *pcs);
+
 void phylink_mac_change(struct phylink *, bool up);
 void phylink_pcs_change(struct phylink_pcs *, bool up);
 
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 05/11] net: pcs: implement Firmware node support for PCS driver
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
                   ` (3 preceding siblings ...)
  2025-05-10 10:23 ` [net-next PATCH v3 04/11] net: phylink: add phylink_release_pcs() to externally release a PCS Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 06/11] net: phylink: support late PCS provider attach Christian Marangi
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Implement the foundation of Firmware node support for PCS driver.

To support this, implement a simple Provider API where a PCS driver can
expose multiple PCS with an xlate .get function.

PCS driver will have to call fwnode_pcs_add_provider() and pass the
firmware node pointer and a xlate function to return the correct PCS for
the passed #pcs-cells.

This will register the PCS in a global list of providers so that
consumer can access it.

The consumer will then use fwnode_pcs_get() to get the actual PCS by
passing the firmware node pointer and the index for #pcs-cells.

For a simple implementation where #pcs-cells is 0 and the PCS driver
expose a single PCS, the xlate function fwnode_pcs_simple_get() is
provided.

For an advanced implementation a custom xlate function is required.

One removal the PCS driver should first delete itself from the provider
list using fwnode_pcs_del_provider() and then call phylink_release_pcs()
on every PCS the driver provides.

A generic function fwnode_phylink_pcs_parse() is provided for MAC driver
that will declare PCS in DT (or ACPI).
This function will parse "pcs-handle" property and fill the passed array
with the parsed PCS in availabel_pcs up to the passed num_pcs value.
It's also possible to pass NULL as array to only parse the PCS and
update the num_pcs value with the count of scanned PCS.

Co-developed-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/pcs/Kconfig          |   7 ++
 drivers/net/pcs/Makefile         |   1 +
 drivers/net/pcs/core.c           | 201 +++++++++++++++++++++++++++++++
 include/linux/pcs/pcs-provider.h |  41 +++++++
 include/linux/pcs/pcs.h          |  56 +++++++++
 5 files changed, 306 insertions(+)
 create mode 100644 drivers/net/pcs/core.c
 create mode 100644 include/linux/pcs/pcs-provider.h
 create mode 100644 include/linux/pcs/pcs.h

diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index f6aa437473de..2951aa2f4cda 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,13 @@
 
 menu "PCS device drivers"
 
+config FWNODE_PCS
+	tristate
+	depends on (ACPI || OF)
+	depends on PHYLINK
+	help
+		Firmware node PCS accessors
+
 config PCS_XPCS
 	tristate "Synopsys DesignWare Ethernet XPCS"
 	select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b90..e29e57025728 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 # Makefile for Linux PCS drivers
 
+obj-$(CONFIG_FWNODE_PCS)	+= core.o
 pcs_xpcs-$(CONFIG_PCS_XPCS)	:= pcs-xpcs.o pcs-xpcs-plat.o \
 				   pcs-xpcs-nxp.o pcs-xpcs-wx.o
 
diff --git a/drivers/net/pcs/core.c b/drivers/net/pcs/core.c
new file mode 100644
index 000000000000..26d07a2edfce
--- /dev/null
+++ b/drivers/net/pcs/core.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+	struct list_head link;
+
+	struct fwnode_handle *fwnode;
+	struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+				   void *data);
+
+	void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+					  void *data)
+{
+	return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);
+
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+			    struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+						       void *data),
+			    void *data)
+{
+	struct fwnode_pcs_provider *pp;
+
+	if (!fwnode)
+		return 0;
+
+	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		return -ENOMEM;
+
+	pp->fwnode = fwnode_handle_get(fwnode);
+	pp->data = data;
+	pp->get = get;
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_add(&pp->link, &fwnode_pcs_providers);
+	mutex_unlock(&fwnode_pcs_mutex);
+	pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+	fwnode_dev_initialized(fwnode, true);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)
+{
+	struct fwnode_pcs_provider *pp;
+
+	if (!fwnode)
+		return;
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_for_each_entry(pp, &fwnode_pcs_providers, link) {
+		if (pp->fwnode == fwnode) {
+			list_del(&pp->link);
+			fwnode_dev_initialized(pp->fwnode, false);
+			fwnode_handle_put(pp->fwnode);
+			kfree(pp);
+			break;
+		}
+	}
+	mutex_unlock(&fwnode_pcs_mutex);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode, int index,
+				const char *name,
+				struct fwnode_reference_args *out_args)
+{
+	int ret;
+
+	if (!fwnode)
+		return -ENOENT;
+
+	if (name)
+		index = fwnode_property_match_string(fwnode, "pcs-names",
+						     name);
+
+	ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+						 "#pcs-cells",
+						 -1, index, out_args);
+	if (ret || (name && index < 0))
+		return ret;
+
+	return 0;
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+	struct fwnode_pcs_provider *provider;
+	struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
+
+	if (!pcsspec)
+		return ERR_PTR(-EINVAL);
+
+	mutex_lock(&fwnode_pcs_mutex);
+	list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+		if (provider->fwnode == pcsspec->fwnode) {
+			pcs = provider->get(pcsspec, provider->data);
+			if (!IS_ERR(pcs))
+				break;
+		}
+	}
+	mutex_unlock(&fwnode_pcs_mutex);
+
+	return pcs;
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,
+					    int index, const char *con_id)
+{
+	struct fwnode_reference_args pcsspec;
+	struct phylink_pcs *pcs;
+	int ret;
+
+	ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+	if (ret)
+		return ERR_PTR(ret);
+
+	pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+	fwnode_handle_put(pcsspec.fwnode);
+
+	return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
+{
+	return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
+				    unsigned int *num_pcs)
+{
+	struct fwnode_reference_args out_args;
+	int index = 0;
+	int ret;
+
+	while (true) {
+		ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+							 "#pcs-cells",
+							 -1, index, &out_args);
+		/* We expect to reach an -ENOENT error while counting */
+		if (ret)
+			break;
+
+		fwnode_handle_put(out_args.fwnode);
+		index++;
+	}
+
+	/* Update num_pcs with parsed PCS */
+	*num_pcs = index;
+
+	/* Return error if we didn't found any PCS */
+	return index > 0 ? 0 : -ENOENT;
+}
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+			     struct phylink_pcs **available_pcs,
+			     unsigned int *num_pcs)
+{
+	int i;
+
+	if (!fwnode_property_present(fwnode, "pcs-handle"))
+		return -ENODEV;
+
+	/* With available_pcs NULL, only count the PCS */
+	if (!available_pcs)
+		return fwnode_phylink_pcs_count(fwnode, num_pcs);
+
+	for (i = 0; i < *num_pcs; i++) {
+		struct phylink_pcs *pcs;
+
+		pcs = fwnode_pcs_get(fwnode, i);
+		if (IS_ERR(pcs))
+			return PTR_ERR(pcs);
+
+		available_pcs[i] = pcs;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 000000000000..2fcc1d696c97
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+/**
+ * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns the PCS. (pointed by data)
+ */
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+					  void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @np: Firmware node
+ * @get: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS to the global providers list
+ * for the firmware node. A function to get the PCS from
+ * firmware node with the use fwnode reference arguments.
+ * To the get function is also passed the interface type
+ * requested for the PHY. PCS driver will use the passed
+ * interface to understand if the PCS can support it or not.
+ *
+ * Returns 0 on success or -ENOMEM on allocation failure.
+ */
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+			    struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+						       void *data),
+			    void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @fwnode: Firmware node
+ */
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 000000000000..c7a4d63bcd6d
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+				   int index);
+
+/**
+ * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: where to store count of parsed PCS
+ *
+ * Generic helper function to fill available_pcs array with PCS parsed
+ * from a "pcs-handle" fwnode property defined in firmware node up to
+ * passed num_pcs.
+ *
+ * If available_pcs is NULL, num_pcs is updated with the count of the
+ * parsed PCS.
+ *
+ * Returns 0 or a negative error.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+			     struct phylink_pcs **available_pcs,
+			     unsigned int *num_pcs);
+#else
+static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+						 int index)
+{
+	return ERR_PTR(-ENOENT);
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+					   struct phylink_pcs **available_pcs,
+					   unsigned int *num_pcs)
+{
+	return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 06/11] net: phylink: support late PCS provider attach
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
                   ` (4 preceding siblings ...)
  2025-05-10 10:23 ` [net-next PATCH v3 05/11] net: pcs: implement Firmware node support for PCS driver Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 07/11] dt-bindings: net: ethernet-controller: permit to define multiple PCS Christian Marangi
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Add support for late PCS provider attachment to a phylink instance.
This works by creating a global notifier for the PCS provider and
making each phylink instance that makes use of fwnode subscribe to
this notifier.

The PCS notifier will emit the event FWNODE_PCS_PROVIDER_ADD every time
a new PCS provider is added.

phylink will then react to this event and will call the new function
fwnode_phylink_pcs_get_from_fwnode() that will check if the PCS fwnode
provided by the event is present in the phy-handle property of the
phylink instance.

If a related PCS is found, then such PCS is added to the phylink
instance PCS list.

Then we link the PCS to the phylink instance if it's not disable and we
refresh the supported interfaces of the phylink instance.

Finally we check if we are in a major_config_failed scenario and trigger
an interface reconfiguration in the next phylink resolve.

In the example scenario where the link was previously torn down due to
removal of PCS, the link will be established again as the PCS came back
and is now available to phylink.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/pcs/core.c    | 40 ++++++++++++++++++++++++++++++
 drivers/net/phy/phylink.c | 52 +++++++++++++++++++++++++++++++++++++++
 include/linux/pcs/pcs.h   | 48 ++++++++++++++++++++++++++++++++++++
 3 files changed, 140 insertions(+)

diff --git a/drivers/net/pcs/core.c b/drivers/net/pcs/core.c
index 26d07a2edfce..409d06658167 100644
--- a/drivers/net/pcs/core.c
+++ b/drivers/net/pcs/core.c
@@ -22,6 +22,13 @@ struct fwnode_pcs_provider {
 
 static LIST_HEAD(fwnode_pcs_providers);
 static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
 
 struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
 					  void *data)
@@ -55,6 +62,10 @@ int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
 
 	fwnode_dev_initialized(fwnode, true);
 
+	blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+				     FWNODE_PCS_PROVIDER_ADD,
+				     fwnode);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
@@ -147,6 +158,35 @@ struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
 }
 EXPORT_SYMBOL_GPL(fwnode_pcs_get);
 
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode)
+{
+	struct fwnode_reference_args pcsspec;
+	int index = 0;
+	int ret;
+
+	/* Loop until we find a matching PCS node or
+	 * fwnode_parse_pcsspec() returns error
+	 * if we don't have any other PCS reference to check.
+	 */
+	while (true) {
+		ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+		if (ret)
+			return ERR_PTR(ret);
+
+		/* Exit loop if we found the matching PCS node */
+		if (pcsspec.fwnode == pcs_fwnode)
+			break;
+
+		/* Check the next PCS reference */
+		index++;
+	}
+
+	return fwnode_pcs_get(fwnode, index);
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_get_from_fwnode);
+
 static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
 				    unsigned int *num_pcs)
 {
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 2f28c4c83062..1a4df0d24aa2 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
 #include <linux/netdevice.h>
 #include <linux/of.h>
 #include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
 #include <linux/phy.h>
 #include <linux/phy_fixed.h>
 #include <linux/phylink.h>
@@ -61,6 +62,7 @@ struct phylink {
 
 	/* List of available PCS */
 	struct list_head pcs_list;
+	struct notifier_block fwnode_pcs_nb;
 
 	/* What interface are supported by the current link.
 	 * Can change on removal or addition of new PCS.
@@ -1909,6 +1911,51 @@ int phylink_set_fixed_link(struct phylink *pl,
 }
 EXPORT_SYMBOL_GPL(phylink_set_fixed_link);
 
+static int pcs_provider_notify(struct notifier_block *self,
+			       unsigned long val, void *data)
+{
+	struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+	struct fwnode_handle *pcs_fwnode = data;
+	struct phylink_pcs *pcs;
+
+	/* Check if the just added PCS provider is
+	 * in the phylink instance phy-handle property
+	 */
+	pcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl->config->dev),
+						 pcs_fwnode);
+	if (IS_ERR(pcs))
+		return NOTIFY_DONE;
+
+	/* Add the PCS */
+	rtnl_lock();
+
+	list_add(&pcs->list, &pl->pcs_list);
+
+	/* Link phylink if we are started */
+	if (!pl->phylink_disable_state)
+		pcs->phylink = pl;
+
+	/* Refresh supported interfaces */
+	phy_interface_copy(pl->supported_interfaces,
+			   pl->config->supported_interfaces);
+	list_for_each_entry(pcs, &pl->pcs_list, list)
+		phy_interface_or(pl->supported_interfaces,
+				 pl->supported_interfaces,
+				 pcs->supported_interfaces);
+
+	mutex_lock(&pl->state_mutex);
+	/* Force an interface reconfig if major config fail */
+	if (pl->major_config_failed)
+		pl->reconfig_interface = true;
+	mutex_unlock(&pl->state_mutex);
+
+	rtnl_unlock();
+
+	phylink_run_resolve(pl);
+
+	return NOTIFY_OK;
+}
+
 /**
  * phylink_create() - create a phylink instance
  * @config: a pointer to the target &struct phylink_config
@@ -1963,6 +2010,11 @@ struct phylink *phylink_create(struct phylink_config *config,
 				 pl->supported_interfaces,
 				 pcs->supported_interfaces);
 
+	if (!phy_interface_empty(config->pcs_interfaces)) {
+		pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+		register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+	}
+
 	pl->config = config;
 	if (config->type == PHYLINK_NETDEV) {
 		pl->netdev = to_net_dev(config->dev);
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
index c7a4d63bcd6d..480c155a3f03 100644
--- a/include/linux/pcs/pcs.h
+++ b/include/linux/pcs/pcs.h
@@ -4,7 +4,24 @@
 
 #include <linux/phylink.h>
 
+enum fwnode_pcs_notify_event {
+	FWNODE_PCS_PROVIDER_ADD,
+};
+
 #if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ *				  PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
 /**
  * fwnode_pcs_get - Retrieves a PCS from a firmware node
  * @fwnode: firmware node
@@ -20,6 +37,25 @@
 struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
 				   int index);
 
+/**
+ * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
+ *					by the firmware node from a
+ *					firmware node
+ * @fwnode: firmware node
+ * @pcs_fwnode: PCS firmware node
+ *
+ * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
+ * 'pcs_fwnode' firmware node.
+ *
+ * Returns a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode);
+
 /**
  * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
  * @fwnode: firmware node
@@ -39,12 +75,24 @@ int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
 			     struct phylink_pcs **available_pcs,
 			     unsigned int *num_pcs);
 #else
+static int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+	return -EOPNOTSUPP;
+}
+
 static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
 						 int index)
 {
 	return ERR_PTR(-ENOENT);
 }
 
+static struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+				   struct fwnode_handle *pcs_fwnode)
+{
+	return ERR_PTR(-ENOENT);
+}
+
 static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
 					   struct phylink_pcs **available_pcs,
 					   unsigned int *num_pcs)
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 07/11] dt-bindings: net: ethernet-controller: permit to define multiple PCS
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
                   ` (5 preceding siblings ...)
  2025-05-10 10:23 ` [net-next PATCH v3 06/11] net: phylink: support late PCS provider attach Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 08/11] net: phylink: add .pcs_link_down PCS OP Christian Marangi
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
can be defined for an ethrnet-controller node to support various PHY
interface mode type.

It's very common for SoCs to have a 2 or more dedicated PCS for Base-X
(for example SGMII, 1000base-x, 2500base-x, ...) and Base-R (for example
USXGMII,10base-r, ...) with the MAC selecting one of the other based on
the attached PHY.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 7cbf11bbe99c..60605b34d242 100644
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -84,8 +84,6 @@ properties:
 
   pcs-handle:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-    items:
-      maxItems: 1
     description:
       Specifies a reference to a node representing a PCS PHY device on a MDIO
       bus to link with an external PHY (phy-handle) if exists.
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 08/11] net: phylink: add .pcs_link_down PCS OP
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
                   ` (6 preceding siblings ...)
  2025-05-10 10:23 ` [net-next PATCH v3 07/11] dt-bindings: net: ethernet-controller: permit to define multiple PCS Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 09/11] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Permit for PCS driver to define specific operation to torn down the link
between the MAC and the PCS.

This might be needed for some PCS that reset counter or require special
reset to correctly work if the link needs to be restored later.

On phylink_link_down() call, the additional phylink_pcs_link_down() will
be called before .mac_link_down to torn down the link.

PCS driver will need to define .pcs_link_down to make use of this.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/phy/phylink.c | 8 ++++++++
 include/linux/phylink.h   | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 1a4df0d24aa2..39cd15e30598 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -1009,6 +1009,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
 		pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
 }
 
+static void phylink_pcs_link_down(struct phylink_pcs *pcs)
+{
+	if (pcs && pcs->ops->pcs_link_down)
+		pcs->ops->pcs_link_down(pcs);
+}
+
 static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)
 {
 	if (pcs && pcs->ops->pcs_disable_eee)
@@ -1686,6 +1692,8 @@ static void phylink_link_down(struct phylink *pl)
 
 	phylink_deactivate_lpi(pl);
 
+	phylink_pcs_link_down(pl->pcs);
+
 	pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
 				   pl->cur_interface);
 	phylink_info(pl, "Link is Down\n");
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index c5496c063b6a..8b3d1dfb83a1 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -494,6 +494,7 @@ struct phylink_pcs {
  * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
  * @pcs_link_up: program the PCS for the resolved link configuration
  *               (where necessary).
+ * @pcs_link_down: torn down link between MAC and PCS.
  * @pcs_disable_eee: optional notification to PCS that EEE has been disabled
  *		     at the MAC.
  * @pcs_enable_eee: optional notification to PCS that EEE will be enabled at
@@ -521,6 +522,7 @@ struct phylink_pcs_ops {
 	void (*pcs_an_restart)(struct phylink_pcs *pcs);
 	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
 			    phy_interface_t interface, int speed, int duplex);
+	void (*pcs_link_down)(struct phylink_pcs *pcs);
 	void (*pcs_disable_eee)(struct phylink_pcs *pcs);
 	void (*pcs_enable_eee)(struct phylink_pcs *pcs);
 	int (*pcs_pre_init)(struct phylink_pcs *pcs);
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 09/11] net: pcs: airoha: add PCS driver for Airoha SoC
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
                   ` (7 preceding siblings ...)
  2025-05-10 10:23 ` [net-next PATCH v3 08/11] net: phylink: add .pcs_link_down PCS OP Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 10/11] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4 Christian Marangi
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Add PCS driver for Airoha SoC for Ethernet Serdes and PCS and permit
usage of external PHY or connected SFP cage. Supported modes are
USXGMII, 10-BASER, 2500BASE-X, 1000BASE-X and SGMII.

The driver register as a PCS provider and supports poll mode to detect
PCS port state. While interrupt is supported by the HW, there are some
defect with the interrupt not fired on cable detach.

The PCS require complex calibration to correctly work and might require
multiple try until the signal detection module "lock" on the signal
level to correct work with the attached PHY.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/pcs/Kconfig      |    7 +
 drivers/net/pcs/Makefile     |    1 +
 drivers/net/pcs/pcs-airoha.c | 2920 ++++++++++++++++++++++++++++++++++
 3 files changed, 2928 insertions(+)
 create mode 100644 drivers/net/pcs/pcs-airoha.c

diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index 2951aa2f4cda..69d28cd1e624 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -12,6 +12,13 @@ config FWNODE_PCS
 	help
 		Firmware node PCS accessors
 
+config PCS_AIROHA
+	select FWNODE_PCS
+	tristate "Airoha PCS driver"
+	help
+	  This module provides helper to phylink for managing the Airoha
+	  PCS for SoC Ethernet Serdes and PCS.
+
 config PCS_XPCS
 	tristate "Synopsys DesignWare Ethernet XPCS"
 	select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index e29e57025728..ae679c8aa571 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -2,6 +2,7 @@
 # Makefile for Linux PCS drivers
 
 obj-$(CONFIG_FWNODE_PCS)	+= core.o
+obj-$(CONFIG_PCS_AIROHA)	+= pcs-airoha.o
 pcs_xpcs-$(CONFIG_PCS_XPCS)	:= pcs-xpcs.o pcs-xpcs-plat.o \
 				   pcs-xpcs-nxp.o pcs-xpcs-wx.o
 
diff --git a/drivers/net/pcs/pcs-airoha.c b/drivers/net/pcs/pcs-airoha.c
new file mode 100644
index 000000000000..43c5c637be37
--- /dev/null
+++ b/drivers/net/pcs/pcs-airoha.c
@@ -0,0 +1,2920 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/rtnetlink.h>
+
+/* SCU*/
+#define AIROHA_SCU_WAN_CONF			0x70
+#define   AIROHA_SCU_WAN_SEL			GENMASK(7, 0)
+#define   AIROHA_SCU_WAN_SEL_SGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
+#define   AIROHA_SCU_WAN_SEL_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
+#define   AIROHA_SCU_WAN_SEL_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
+#define AIROHA_SCU_SSR3				0x94
+#define   AIROHA_SCU_ETH_XSI_SEL		GENMASK(14, 13)
+#define   AIROHA_SCU_ETH_XSI_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
+#define   AIROHA_SCU_ETH_XSI_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
+#define AIROHA_SCU_SSTR				0x9c
+#define   AIROHA_SCU_PON_XSI_SEL		GENMASK(10, 9)
+#define   AIROHA_SCU_PON_XSI_USXGMII		FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
+#define   AIROHA_SCU_PON_XSI_HSGMII		FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
+
+/* XFI_MAC */
+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG		0x0
+#define   AIROHA_PCS_XFI_RX_FRAG_LEN		GENMASK(26, 22)
+#define   AIROHA_PCS_XFI_TX_FRAG_LEN		GENMASK(21, 17)
+#define   AIROHA_PCS_XFI_IPG_NUM		GENMASK(15, 10)
+#define   AIROHA_PCS_XFI_TX_FC_EN		BIT(5)
+#define   AIROHA_PCS_XFI_RX_FC_EN		BIT(4)
+#define   AIROHA_PCS_XFI_RXMPI_STOP		BIT(3)
+#define   AIROHA_PCS_XFI_RXMBI_STOP		BIT(2)
+#define   AIROHA_PCS_XFI_TXMPI_STOP		BIT(1)
+#define   AIROHA_PCS_XFI_TXMBI_STOP		BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST	0x10
+#define   AIROHA_PCS_XFI_MAC_LOGIC_RST		BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH		0x60
+#define   AIROHA_PCS_XFI_MAC_MACADDRH		GENMASK(15, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL		0x64
+#define   AIROHA_PCS_XFI_MAC_MACADDRL		GENMASK(31, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR		0x100
+#define   AIROHA_PCS_XFI_GLB_CNT_CLR		BIT(0)
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0	0x0
+#define   AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE	BIT(12)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART	BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1	0x4 /* BMSR */
+#define   AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4	0x10
+#define   AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5	0x14 /* LPA */
+#define   AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11	0x2c
+#define   AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER	GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13	0x34
+#define   AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define   AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
+#define     AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
+#define     AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
+#define     AIROHA_PCS_HSGMII_AN_SIDEBAND_EN	BIT(1)
+#define     AIROHA_PCS_HSGMII_AN_SGMII_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
+#define   AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE	BIT(0)
+
+/* HSGMII_PCS */
+#define AIROHA_PCS_HSGMII_PCS_CTROL_1		0x0
+#define   AIROHA_PCS_TBI_10B_MODE		BIT(30)
+#define   AIROHA_PCS_SGMII_SEND_AN_ERR_EN	BIT(24)
+#define   AIROHA_PCS_REMOTE_FAULT_DIS		BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_3		0x8
+#define   AIROHA_PCS_HSGMII_PCS_LINK_STSTIME	GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_6		0x14
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
+#define   AIROHA_PCS_HSGMII_PCS_MAC_MODE	BIT(8)
+#define   AIROHA_PCS_HSGMII_PCS_TX_ENABLE	BIT(4)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT	BIT(1)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
+#define   AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
+#define   AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT	BIT(4)
+#define   AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
+#define   AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
+#define   AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT	BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
+#define ARIOHA_PCS_HSGMII_PCS_STATE_2		0x104
+#define   AIROHA_PCS_HSGMII_PCS_RX_SYNC		BIT(5)
+#define   AIROHA_PCS_HSGMII_PCS_AN_DONE		BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_INT_STATE		0x15c
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS	BIT(3)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC	BIT(1)
+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE	BIT(0)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0	0x14
+#define   AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0	BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
+#define   AIROHA_PCS_LINK_MODE_P0		GENMASK(5, 4)
+#define   AIROHA_PCS_LINK_MODE_P0_2_5G		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
+#define   AIROHA_PCS_LINK_MODE_P0_1G		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
+#define   AIROHA_PCS_LINK_MODE_P0_100M		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
+#define   AIROHA_PCS_LINK_MODE_P0_10M		FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
+#define   AIROHA_PCS_FORCE_SPD_MODE_P0		BIT(2)
+#define   AIROHA_PCS_FORCE_LINKDOWN_P0		BIT(1)
+#define   AIROHA_PCS_FORCE_LINKUP_P0		BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0	0x100
+#define   AIROHA_PCS_HSGMII_XFI_SEL		BIT(28)
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL	0x14c
+#define   AIROHA_PCS_HSGMII_PCS_INT		BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15	0x43c
+#define   AIROHA_PCS_LINK_STS_P0		BIT(3)
+#define   AIROHA_PCS_SPEED_STS_P0		GENMASK(2, 0)
+#define   AIROHA_PCS_SPEED_STS_P0_1G		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
+#define   AIROHA_PCS_SPEED_STS_P0_100M		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
+#define   AIROHA_PCS_SPEED_STS_P0_10M		FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18	0x448
+#define   AIROHA_PCS_P0_SGMII_IS_10		BIT(2)
+#define   AIROHA_PCS_P0_SGMII_IS_100		BIT(1)
+#define   AIROHA_PCS_P0_SGMII_IS_1000		BIT(0)
+
+/* HSGMII_RATE_ADP */
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0	0x0
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN	BIT(4)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN	BIT(0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1	0x4
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6	0x18
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8	0x20
+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11	0x2c
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
+	FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0	0x100
+#define   AIROHA_PCS_HSGMII_P0_DIS_MII_MODE	BIT(31)
+
+/* USXGMII */
+#define AIROHA_PCS_USXGMII_PCS_CTROL_1		0x0
+#define   AIROHA_PCS_USXGMII_SPEED_SEL_H	BIT(13)
+#define AIROHA_PCS_USXGMII_PCS_STUS_1		0x30
+#define   AIROHA_PCS_USXGMII_RX_LINK_STUS	BIT(12)
+#define   AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
+#define   AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
+#define   AIROHA_PCS_USXGMII_PCS_BLK_LK		BIT(0)
+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116	0x22c
+#define AIROHA_PCS_USXGMII_PCS_CTRL_0		0x2c0
+#define   AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN	BIT(24)
+#define   AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_1		0x2c4
+#define   AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN	BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
+#define   AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_2		0x2c8
+#define   AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN	BIT(16)
+#define   AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_3		0x2cc
+#define   AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
+#define   AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
+#define   AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN	BIT(8)
+#define   AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2	0x2d8
+#define   AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
+#define   AIROHA_PCS_USXGMII_R_TYPE_E_INT	BIT(16)
+#define   AIROHA_PCS_USXGMII_R_TYPE_T_INT	BIT(8)
+#define   AIROHA_PCS_USXGMII_R_TYPE_D_INT	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3	0x2dc
+#define   AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
+#define   AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
+#define   AIROHA_PCS_USXGMII_LINK_UP_ST_INT	BIT(8)
+#define   AIROHA_PCS_USXGMII_HI_BER_ST_INT	BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_4		0x2e0
+#define   AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4	0x2e4
+#define   AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0	0x2f8
+#define   AIROHA_PCS_USXGMII_AN_RESTART		BIT(8)
+#define   AIROHA_PCS_USXGMII_AN_ENABLE		BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0	0x310
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE	GENMASK(30, 28)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
+#define   AIROHA_PCS_USXGMII_PARTNER_ABILITY	GENMASK(15, 0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2	0x318
+#define   AIROHA_PCS_USXGMII_PCS_AN_COMPLETE	BIT(24)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6	0x31c
+#define   AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7	0x320
+#define   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE	BIT(12)
+#define   AIROHA_PCS_USXGMII_MODE		GENMASK(10, 8)
+#define   AIROHA_PCS_USXGMII_MODE_10000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x0)
+#define   AIROHA_PCS_USXGMII_MODE_5000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x1)
+#define   AIROHA_PCS_USXGMII_MODE_2500		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x2)
+#define   AIROHA_PCS_USXGMII_MODE_1000		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x3)
+#define   AIROHA_PCS_USXGMII_MODE_100		FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x4)
+
+/* PMA_PHYA */
+#define AIROHA_PCS_ANA_PXP_CMN_EN		0x0
+#define   AIROHA_PCS_ANA_CMN_EN			BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN	0x4
+#define   AIROHA_PCS_ANA_JCPLL_CHP_IOFST	GENMASK(29, 24)
+#define   AIROHA_PCS_ANA_JCPLL_CHP_IBIAS	GENMASK(21, 16)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN	BIT(8)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR		0x8
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BWR		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BP		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BC		GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BR		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC	0xc
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_DIV	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_CODE	GENMASK(23, 16)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_OPTION	BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_LPF_BWC		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC	0x10
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KS		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KF		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KFC	GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
+#define   AIROHA_PCS_ANA_JCPLL_POSTDIV_D5	BIT(24)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE	GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3)
+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY	0x1c
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_PLL_RSTB		BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY		GENMASK(2, 0)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5)
+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM	0x20
+#define   AIROHA_PCS_ANA_JCPLL_SDM_OUT		BIT(24)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_MODE		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_IFM		BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN	0x24
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF	GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN	GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN	BIT(8)
+#define   AIROHA_PCS_ANA_JCPLL_SDM_HREN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN	0x28
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW	GENMASK(26, 24)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV		0x2c
+#define   AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN	BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_CFIX		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV		GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV_1		FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0)
+#define   AIROHA_PCS_ANA_JCPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR	0x30
+#define   AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI	BIT(17)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_EN		BIT(16)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
+#define   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR	GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN	0x34
+#define   AIROHA_PCS_ANA_JCPLL_SSC_DELTA1	GENMASK(23, 8)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA	0x38
+#define   AIROHA_PCS_ANA_JCPLL_SSC_PERIOD	GENMASK(31, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SSC_DELTA	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H	0x48
+#define   AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_JCPLL_SPARE_L		GENMASK(15, 8)
+#define     AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO	FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS	0x50
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BC		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BR		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_TXPLL_CHP_IOFST	GENMASK(13, 8)
+#define   AIROHA_PCS_ANA_TXPLL_CHP_IBIAS	GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP		0x54
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_OPTION	BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BWC		GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BWR		GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_TXPLL_LPF_BP		GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE	0x58
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KF		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KFC	GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_DIV	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_CODE	GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS	0x5c
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE	GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_POSTDIV_EN	BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KS		GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL	0x64
+#define   AIROHA_PCS_ANA_TXPLL_PLL_RSTB		BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_RST_DLY		GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV	GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN	0x68
+#define   AIROHA_PCS_ANA_TXPLL_SDM_MODE		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_IFM		BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS	GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD	0x6c
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN	BIT(24)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_HREN		BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_OUT		BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD		GENMASK(1, 0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN	0x70
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF	GENMASK(12, 8)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN	GENMASK(2, 0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN	0x74
+#define   AIROHA_PCS_ANA_TXPLL_VCO_CFIX		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_1		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_2		FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16	FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6)
+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN	0x78
+#define   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR	GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN		0x7c
+#define   AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN	BIT(16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI	BIT(8)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_EN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1	0x80
+#define   AIROHA_PCS_ANA_TXPLL_SSC_DELTA	GENMASK(31, 16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_DELTA1	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD	0x84
+#define   AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_TXPLL_LDO_OUT		GENMASK(17, 16)
+#define   AIROHA_PCS_ANA_TXPLL_SSC_PERIOD	GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF	0x94
+#define   AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF	GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN		0xc4
+#define   AIROHA_PCS_ANA_TX_DMEDGEGEN_EN	BIT(24)
+#define   AIROHA_PCS_ANA_TX_CKLDO_EN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL	0xcc
+#define    AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE	BIT(24)
+#define    AIROHA_PCS_ANA_RX_PHY_CK_SEL		BIT(16) /* 0: from PR 1: from DES */
+#define AIROHA_PCS_ANA_PXP_RX_REV_0		0xd4
+#define   AIROHA_PCS_ANA_RX_REV_1		GENMASK(31, 16)
+#define     AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define     AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define     AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define     AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK	GENMASK(19, 18)
+#define     AIROHA_PCS_ANA_REV_1_FECUR_PWDB	BIT(16)
+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV		0xd8
+#define   AIROHA_PCS_ANA_RX_TDC_CK_SEL		BIT(24)
+#define   AIROHA_PCS_ANA_RX_PHYCK_RSTB		BIT(16)
+#define   AIROHA_PCS_ANA_RX_PHYCK_SEL		GENMASK(9, 8)
+#define   AIROHA_PCS_ANA_RX_PHYCK_DIV		GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
+#define   AIROHA_PCS_ANA_CDR_PD_EDGE_DIS	BIT(8)
+#define   AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV	BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO	0xe8
+#define   AIROHA_PCS_ANA_CDR_LPF_TOP_LIM	GENMASK(26, 8)
+#define   AIROHA_PCS_ANA_CDR_LPF_RATIO		GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE	0xf4
+#define   AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF	BIT(24)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC	0xf8
+#define   AIROHA_PCS_ANA_CDR_PR_KBAND_DIV	GENMASK(26, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_BETA_SEL	GENMASK(19, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_VCOADC_OS	GENMASK(11, 8)
+#define   AIROHA_PCS_ANA_CDR_PR_BETA_DAC	GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
+#define   AIROHA_PCS_ANA_CDR_PR_FBKSEL		GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL	GENMASK(10, 8)
+#define   AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL	GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN	0x10c
+#define   AIROHA_PCS_ANA_RX_DAC_MON		GENMASK(28, 24)
+#define   AIROHA_PCS_ANA_CDR_PR_CAP_EN		BIT(19)
+#define   AIROHA_PCS_ANA_CDR_BUF_IN_SR		GENMASK(18, 16)
+#define   AIROHA_PCS_ANA_CDR_PR_XFICK_EN	BIT(2)
+#define   AIROHA_PCS_ANA_CDR_PR_MONDPI_EN	BIT(1)
+#define   AIROHA_PCS_ANA_CDR_PR_MONDPR_EN	BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE		0x110
+#define   AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL	GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH	0x114
+#define   AIROHA_PCS_ANA_RX_FE_50OHMS_SEL	GENMASK(25, 24)
+#define   AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL	GENMASK(20, 16)
+#define   AIROHA_PCS_ANA_RX_SIGDET_PEAK		GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN	0x118
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN	BIT(24)
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN	BIT(16)
+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN	BIT(8)
+#define   AIROHA_PCS_ANA_RX_FE_EQ_HZEN		BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB	0x11c
+#define   AIROHA_PCS_ANA_FE_VCM_GEN_PWDB	BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW	0x120
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE		GENMASK(17, 8)
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8))
+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9))
+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE		0x13c
+#define   AIROHA_PCS_ANA_AEQ_OFORCE		GENMASK(19, 8)
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_SAOS	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_VGA		FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_CTLE	FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9))
+#define   AIROHA_PCS_ANA_AEQ_OFORCE_ATT		FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10))
+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
+#define   AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ	BIT(24)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ	0x148
+#define   AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ	BIT(24)
+#define   AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ	BIT(16)
+#define   AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ	BIT(8)
+#define   AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ	BIT(0)
+
+/* PMA_PHYD */
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0	0x0
+#define   AIROHA_PCS_PMA_SW_LCPLL_EN		BIT(24)
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1	0x4
+#define   AIROHA_PCS_PMA_LCPLL_MAN_PWDB		BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2	0x88
+#define   AIROHA_PCS_PMA_DATA_SHIFT		BIT(8)
+#define   AIROHA_PCS_PMA_EYECNT_FAST		BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0	0x8c
+#define   AIROHA_PCS_PMA_RX_OS_START		GENMASK(23, 8)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT		GENMASK(2, 0)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4	FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1	0x90
+#define   AIROHA_PCS_PMA_RX_PICAL_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_PICAL_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2	0x94
+#define   AIROHA_PCS_PMA_RX_PDOS_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_PDOS_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3	0x98
+#define   AIROHA_PCS_PMA_RX_FEOS_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_FEOS_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4	0x9c
+#define   AIROHA_PCS_PMA_RX_SDCAL_END		GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_SDCAL_START		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5	0x100
+#define   AIROHA_PCS_PMA_RX_RDY			GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_RX_BLWC_RDY_EN		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6	0x104
+#define   AIROHA_PCS_PMA_RX_OS_END		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
+#define   AIROHA_PCS_PMA_DISB_RX_RDY		BIT(24)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
+#define   AIROHA_PCS_PMA_FORCE_RX_RDY		BIT(24)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_3		0x120
+#define   AIROHA_PCS_PMA_EQ_DEBUG_SEL		GENMASK(17, 16)
+#define   AIROHA_PCS_PMA_FOM_NUM_ORDER		GENMASK(12, 8)
+#define   AIROHA_PCS_PMA_A_SEL			GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1		0x14c
+#define   AIROHA_PCS_PMA_UNLOCK_CYCLECNT	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_LOCK_CYCLECNT		GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2		0x150
+#define   AIROHA_PCS_PMA_LOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_LOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3		0x154
+#define   AIROHA_PCS_PMA_UNLOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_UNLOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4		0x158
+#define   AIROHA_PCS_PMA_LOCK_UNLOCKTH		GENMASK(15, 12)
+#define   AIROHA_PCS_PMA_LOCK_LOCKTH		GENMASK(11, 8)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN	GENMASK(2, 0)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT	FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL	FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1		0x16c
+#define   AIROHA_PCS_PMA_SIGDET_EN		BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_1			0x174
+#define   AIROHA_PCS_PMA_LPATH_IDAC		GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_2			0x178
+#define   AIROHA_PCS_PMA_CK_RATE		GENMASK(18, 16)
+#define   AIROHA_PCS_PMA_CK_RATE_20		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
+#define   AIROHA_PCS_PMA_CK_RATE_10		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
+#define   AIROHA_PCS_PMA_CK_RATE_5		FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_RX_FLL_5			0x184
+#define   AIROHA_PCS_PMA_FLL_IDAC_MIN		GENMASK(26, 16)
+#define   AIROHA_PCS_PMA_FLL_IDAC_MAX		GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_B		        0x19c
+#define   AIROHA_PCS_PMA_LOAD_EN		BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_1		0x208
+#define   AIROHA_PCS_PMA_SIGDET_RST_B		BIT(8)
+#define AIROHA_PCS_PMA_TX_RST_B			0x260
+#define   AIROHA_PCS_PMA_TXCALIB_RST_B		BIT(8)
+#define   AIROHA_PCS_PMA_TX_TOP_RST_B		BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_4		0x320
+#define   AIROHA_PCS_PMA_DISB_BLWC_OFFSET	BIT(24)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9		0x330
+#define   AIROHA_PCS_PMA_FORCE_FBCK_LOCK	BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_8		0x33c
+#define   AIROHA_PCS_PMA_DISB_FBCK_LOCK		BIT(0)
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0		0x38c
+#define   AIROHA_PCS_PMA_RX_SYS_EN_SEL		GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0	0x390
+#define   AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1	0x394
+#define   AIROHA_PCS_PMA_PLL_LOCK_TARGET_END	GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG	GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3	0x39c
+#define   AIROHA_PCS_PMA_PLL_LOCK_LOCKTH	GENMASK(11, 8)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL		0x48c
+#define   AIROHA_PCS_PMA_DISB_LEQ		BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0	0x34c
+#define   AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB	BIT(24)
+#define   AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB	BIT(16)
+#define   AIROHA_PCS_PMA_XPON_CDR_PW_PWDB	BIT(8)
+#define   AIROHA_PCS_PMA_XPON_RX_FE_PWDB	BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1	0x350
+#define   AIROHA_PCS_PMA_RX_SIDGET_PWDB		BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_0		0x360
+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2		0x380
+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1	0x374
+#define   AIROHA_PCS_PMA_XPON_RX_RATE_CTRL	GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SW_RST_SET		0x460
+#define   AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N	BIT(11)
+#define   AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N	BIT(10)
+#define   AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N BIT(9)
+#define   AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N	BIT(8)
+#define   AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N	BIT(7)
+#define   AIROHA_PCS_PMA_SW_TX_FIFO_RST_N	BIT(6)
+#define   AIROHA_PCS_PMA_SW_REF_RST_N		BIT(5)
+#define   AIROHA_PCS_PMA_SW_ALLPCS_RST_N	BIT(4)
+#define   AIROHA_PCS_PMA_SW_PMA_RST_N		BIT(3)
+#define   AIROHA_PCS_PMA_SW_TX_RST_N		BIT(2)
+#define   AIROHA_PCS_PMA_SW_RX_RST_N		BIT(1)
+#define   AIROHA_PCS_PMA_SW_RX_FIFO_RST_N	BIT(0)
+#define AIROHA_PCS_PMA_XPON_INT_EN_3		0x474
+#define   AIROHA_PCS_PMA_RX_SIGDET_INT_EN	BIT(16)
+#define AIROHA_PCS_PMA_XPON_INT_STA_3		0x47c
+#define   AIROHA_PCS_PMA_RX_SIGDET_INT		BIT(16)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL		0x48c
+#define   AIROHA_PCS_PMA_DISB_LEQ		BIT(0)
+#define AIROHA_PCS_PMA_RX_FREQDET		0x530
+#define   AIROHA_PCS_PMA_FL_OUT			GENMASK(31, 16)
+#define   AIROHA_PCS_PMA_FBCK_LOCK		BIT(0)
+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL	0x580
+#define   AIROHA_PCS_PMA_PON_TX_RATE_CTRL	GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN	0x768
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL GENMASK(19, 16)
+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED		0x76c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_OSR_SEL	GENMASK(17, 16)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B		0x778
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1	GENMASK(20, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL		0x77c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL	GENMASK(2, 0)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1		0x780
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2	GENMASK(20, 16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL		0x784
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC		0x794
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC	GENMASK(10, 0)
+#define     AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW	0x798
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW	GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS		0x79c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS	BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_FE_VOS	GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW	0x800
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW	GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS		0x80c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON	BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB		0x814
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL	BIT(16)
+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA	0x818
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB		0x81c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN	0x820
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB	0x824
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN	0x828
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B	0x84c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B	 BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN	0x854
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN	BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN		0x874
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL	BIT(16)
+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL		0x88c
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB		0x894
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN	BIT(16)
+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB	 BIT(0)
+
+#define AIROHA_PCS_MAX_CALIBRATION_TRY		50
+#define AIROHA_PCS_MAX_NUM_RSTS			2
+
+enum xfi_port_type {
+	AIROHA_PCS_ETH,
+	AIROHA_PCS_PON,
+};
+
+struct airoha_pcs_match_data {
+	enum xfi_port_type port_type;
+};
+
+struct airoha_pcs_priv {
+	struct device *dev;
+	const struct airoha_pcs_match_data *data;
+	phy_interface_t interface;
+
+	struct regmap *scu;
+
+	struct regmap *xfi_mac;
+	struct regmap *hsgmii_an;
+	struct regmap *hsgmii_pcs;
+	struct regmap *hsgmii_rate_adp;
+	struct regmap *multi_sgmii;
+	struct regmap *usxgmii_pcs;
+
+	struct regmap *xfi_pma;
+	struct regmap *xfi_ana;
+
+	struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
+
+	struct phylink_pcs pcs;
+};
+
+static struct airoha_pcs_priv *phylink_pcs_to_airoha_pcs_port(struct phylink_pcs *pcs)
+{
+	return container_of(pcs, struct airoha_pcs_priv, pcs);
+}
+
+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 xsi_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+	default:
+		xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
+	}
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
+			   AIROHA_SCU_ETH_XSI_SEL,
+			   xsi_sel);
+}
+
+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 xsi_sel, wan_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+	default:
+		wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
+		xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
+	}
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+			   AIROHA_SCU_PON_XSI_SEL,
+			   xsi_sel);
+
+	regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+			   AIROHA_SCU_WAN_SEL,
+			   wan_sel);
+}
+
+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
+				phy_interface_t interface)
+{
+	int ret;
+
+	switch (priv->data->port_type) {
+	case AIROHA_PCS_ETH:
+		airoha_pcs_setup_scu_eth(priv, interface);
+		break;
+	case AIROHA_PCS_PON:
+		airoha_pcs_setup_scu_pon(priv, interface);
+		break;
+	}
+
+	ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
+					priv->rsts);
+	if (ret)
+		return ret;
+
+	ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
+					  priv->rsts);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_set_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			AIROHA_PCS_HSGMII_XFI_SEL);
+
+	/* Disable Hibernation */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+			  AIROHA_PCS_USXGMII_SPEED_SEL_H);
+
+	/* FIXME: wait Airoha */
+	/* Avoid PCS sending garbage to MAC in some HW revision (E0) */
+	regmap_write(priv->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+}
+
+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			  AIROHA_PCS_HSGMII_XFI_SEL);
+
+	regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+			AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv)
+{
+	regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+			  AIROHA_PCS_HSGMII_XFI_SEL);
+
+	regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+			AIROHA_PCS_TBI_10B_MODE);
+
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
+			   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
+
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
+			   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
+}
+
+static void airoha_pcs_init(struct airoha_pcs_priv *priv,
+			    phy_interface_t interface)
+{
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		airoha_pcs_init_sgmii(priv);
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		airoha_pcs_init_hsgmii(priv);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		airoha_pcs_init_usxgmii(priv);
+		break;
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv)
+{
+	/* Disable every interrupt */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			  AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
+			  AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
+			  AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+	/* Clear interrupt */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+			AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+			  AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+			  AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+}
+
+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv)
+{
+	/* Disable every Interrupt */
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
+			  AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
+			  AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
+			  AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
+			  AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
+			  AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
+			  AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
+			  AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
+			  AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
+
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
+			  AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
+
+	/* Clear any pending interrupt */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
+			AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_E_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_T_INT |
+			AIROHA_PCS_USXGMII_R_TYPE_D_INT);
+
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
+			AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
+			AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
+			AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
+			AIROHA_PCS_USXGMII_HI_BER_ST_INT);
+
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
+			AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
+
+	/* Interrupt saddly seems to be not weel supported for Link Down.
+	 * PCS Poll is a must to correctly read and react on Cable Deatch
+	 * as only cable attach interrupt are fired and Link Down interrupt
+	 * are fired only in special case like AN restart.
+	 */
+}
+
+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
+				      phy_interface_t interface)
+{
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		return airoha_pcs_interrupt_init_sgmii(priv);
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		return airoha_pcs_interrupt_init_usxgmii(priv);
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 kband_vref;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		kband_vref = 0x10;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		kband_vref = 0xf;
+		break;
+	default:
+		return;
+	}
+
+	/* Setup LDO */
+	usleep_range(200, 300);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+			AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
+
+	/* Setup RSTB */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			AIROHA_PCS_ANA_JCPLL_PLL_RSTB);
+
+	/* Enable PLL force selection and Force Disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
+
+	/* Setup SDM */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS |
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_EN,
+			   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM,
+			   AIROHA_PCS_ANA_JCPLL_SDM_OUT |
+			   AIROHA_PCS_ANA_JCPLL_SDM_ORD |
+			   AIROHA_PCS_ANA_JCPLL_SDM_MODE |
+			   AIROHA_PCS_ANA_JCPLL_SDM_IFM,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) |
+			   AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_MODE, 0x0));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
+			  AIROHA_PCS_ANA_JCPLL_SDM_HREN);
+
+	/* Setup SSC */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA,
+			   AIROHA_PCS_ANA_JCPLL_SSC_PERIOD |
+			   AIROHA_PCS_ANA_JCPLL_SSC_DELTA,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_PERIOD, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN,
+			   AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 |
+			   AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA1, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
+			   AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI |
+			   AIROHA_PCS_ANA_JCPLL_SSC_EN |
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x0));
+
+	/* Setup LPF */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN,
+			   AIROHA_PCS_ANA_JCPLL_CHP_IOFST |
+			   AIROHA_PCS_ANA_JCPLL_CHP_IBIAS |
+			   AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IOFST, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IBIAS, 0x18));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR,
+			   AIROHA_PCS_ANA_JCPLL_LPF_BWR |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BP |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BC |
+			   AIROHA_PCS_ANA_JCPLL_LPF_BR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWR, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BP, 0x10) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BC, 0x1f) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BR, BIT(3) | BIT(1)));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
+			   AIROHA_PCS_ANA_JCPLL_LPF_BWC,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWC, 0x0));
+
+	/* Setup VCO */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR |
+			   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
+			   AIROHA_PCS_ANA_JCPLL_VCO_CFIX,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR, 0x4) |
+			   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_CFIX, 0x1));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H |
+			   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x3));
+
+	/* Setup PCW */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
+			   AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
+
+	/* Setup DIV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE,
+			   AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 |
+			   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE,
+			   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCODIV,
+			   AIROHA_PCS_ANA_JCPLL_VCODIV_1);
+
+	/* Setup KBand */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC,
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KS |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KF |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_KFC,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KS, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KF, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KFC, 0x0));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
+			   AIROHA_PCS_ANA_JCPLL_KBAND_DIV |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_CODE |
+			   AIROHA_PCS_ANA_JCPLL_KBAND_OPTION,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_DIV, 0x2) |
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_CODE, 0xe4));
+
+	/* Setup TCL */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+			   AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, kband_vref));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF, 0x5) |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 |
+			   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW |
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 |
+			   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN);
+
+	/* Enable PLL */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+
+	/* Enale PLL Output */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
+			AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
+}
+
+static void airoha_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
+				     phy_interface_t interface)
+{
+	u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
+	u32 vco_cfix;
+	u32 pcw;
+	u32 tcl_amp_vref;
+	bool sdm_hren;
+	bool vcodiv;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		lpf_chp_ibias = 0xf;
+		lpf_bp = BIT(1);
+		lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+		lpf_bwc = BIT(4) | BIT(3);
+		vco_cfix = BIT(1) | BIT(0);
+		pcw = BIT(27);
+		tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+		vcodiv = false;
+		sdm_hren = false;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		lpf_chp_ibias = 0xa;
+		lpf_bp = BIT(2) | BIT(0);
+		lpf_bwr = 0;
+		lpf_bwc = 0;
+		vco_cfix = 0;
+		pcw = BIT(27) | BIT(25);
+		tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
+		vcodiv = true;
+		sdm_hren = false;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		lpf_chp_ibias = 0xf;
+		lpf_bp = BIT(1);
+		lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+		lpf_bwc = BIT(4) | BIT(3);
+		vco_cfix = BIT(0);
+		pcw = BIT(27) | BIT(22);
+		tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+		vcodiv = false;
+		sdm_hren = true;
+		break;
+	default:
+		return;
+	}
+
+	/* Setup VCO LDO Output */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+			   AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT |
+			   AIROHA_PCS_ANA_TXPLL_LDO_OUT,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1));
+
+	/* Setup RSTB */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL,
+			   AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+			   AIROHA_PCS_ANA_TXPLL_RST_DLY |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_DIV |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL,
+			   AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 |
+			   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL);
+
+	/* Enable PLL force selection and Force Disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+	/* Setup SDM */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN,
+			   AIROHA_PCS_ANA_TXPLL_SDM_MODE |
+			   AIROHA_PCS_ANA_TXPLL_SDM_IFM |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) |
+			   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+			   AIROHA_PCS_ANA_TXPLL_SDM_HREN |
+			   AIROHA_PCS_ANA_TXPLL_SDM_OUT |
+			   AIROHA_PCS_ANA_TXPLL_SDM_ORD,
+			   (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) |
+			   AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
+
+	/* Setup SSC */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1,
+			   AIROHA_PCS_ANA_TXPLL_SSC_DELTA |
+			   AIROHA_PCS_ANA_TXPLL_SSC_DELTA1,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN,
+			  AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN |
+			  AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI |
+			  AIROHA_PCS_ANA_TXPLL_SSC_EN);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+			   AIROHA_PCS_ANA_TXPLL_SSC_PERIOD,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0));
+
+	/* Setup LPF */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS,
+			   AIROHA_PCS_ANA_TXPLL_LPF_BC |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BR |
+			   AIROHA_PCS_ANA_TXPLL_CHP_IOFST |
+			   AIROHA_PCS_ANA_TXPLL_CHP_IBIAS,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, 0x5) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, lpf_chp_ibias));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+			   AIROHA_PCS_ANA_TXPLL_LPF_BWC |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BWR |
+			   AIROHA_PCS_ANA_TXPLL_LPF_BP,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, lpf_bwc) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, lpf_bp));
+
+	/* Setup VCO */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCO_CFIX,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L |
+			   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H |
+			   AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR |
+			   AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR |
+			   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) |
+			   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN);
+
+	/* Setup PCW */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+			   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+	/* Setup KBand */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE,
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KF |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KFC |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_DIV |
+			   AIROHA_PCS_ANA_TXPLL_KBAND_CODE,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+			   AIROHA_PCS_ANA_TXPLL_KBAND_KS,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1));
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+			  AIROHA_PCS_ANA_TXPLL_KBAND_OPTION);
+
+	/* Setup DIV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+			   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE |
+			   AIROHA_PCS_ANA_TXPLL_POSTDIV_EN,
+			   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_VCODIV,
+			   vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+				    AIROHA_PCS_ANA_TXPLL_VCODIV_1);
+
+	/* Setup TCL */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+			   AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF |
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN,
+			   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) |
+			   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW |
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN,
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 |
+			   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+			AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN);
+
+	/* Enable PLL */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+	/* Enale PLL Output */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+			AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+}
+
+static void airoha_pcs_pll_bringup(struct airoha_pcs_priv *priv,
+				   phy_interface_t interface)
+{
+	airoha_pcs_jcpll_bringup(priv, interface);
+
+	usleep_range(200, 300);
+
+	airoha_pcs_txpll_bringup(priv, interface);
+
+	usleep_range(200, 300);
+}
+
+static void airoha_pcs_tx_bringup(struct airoha_pcs_priv *priv,
+				  phy_interface_t interface)
+{
+	u32 tx_rate_ctrl;
+	u32 ckin_divisor;
+	u32 fir_cn1, fir_c0b, fir_c1;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		ckin_divisor = BIT(1);
+		tx_rate_ctrl = BIT(0);
+		fir_cn1 = 0;
+		fir_c0b = 12;
+		fir_c1 = 0;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		ckin_divisor = BIT(2);
+		tx_rate_ctrl = BIT(0);
+		fir_cn1 = 0;
+		fir_c0b = 11;
+		fir_c1 = 1;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		ckin_divisor = BIT(2) | BIT(0);
+		tx_rate_ctrl = BIT(1);
+		fir_cn1 = 1;
+		fir_c0b = 1;
+		fir_c1 = 11;
+		break;
+	default:
+		return;
+	}
+
+	/* Set TX rate ctrl */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+				      tx_rate_ctrl));
+
+	/* Setup TX Config */
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN,
+			AIROHA_PCS_ANA_TX_DMEDGEGEN_EN |
+			AIROHA_PCS_ANA_TX_CKLDO_EN);
+
+	udelay(1);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+			AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+	/* FIXME: Ask Airoha TX term is OK to reset? */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+				      ckin_divisor) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+				      tx_rate_ctrl));
+
+	/* Setup TX FIR Load Parameters (Reference 660mV) */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+			   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+	/* Reset TX Bar */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_RST_B,
+			AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
+}
+
+static void airoha_pcs_rx_bringup(struct airoha_pcs_priv *priv,
+				  phy_interface_t interface)
+{
+	u32 rx_rate_ctrl;
+	u32 osr;
+	u32 pr_cdr_beta_dac;
+	u32 cdr_pr_buf_in_sr;
+	bool cdr_pr_cap_en;
+	u32 sigdet_vth_sel;
+	u32 phyck_div, phyck_sel;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+		osr = BIT(1) | BIT(0); /* 1.25G */
+		pr_cdr_beta_dac = BIT(3);
+		rx_rate_ctrl = 0;
+		cdr_pr_cap_en = false;
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+		sigdet_vth_sel = BIT(2) | BIT(1);
+		phyck_div = BIT(5) | BIT(3) | BIT(0);
+		phyck_sel = BIT(0);
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX:
+		osr = BIT(0); /* 2.5G */
+		pr_cdr_beta_dac = BIT(2) | BIT(1);
+		rx_rate_ctrl = 0;
+		cdr_pr_cap_en = true;
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1);
+		sigdet_vth_sel = BIT(2) | BIT(1);
+		phyck_div = BIT(3) | BIT(1) | BIT(0);
+		phyck_sel = BIT(0);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		osr = 0; /* 10G */
+		cdr_pr_cap_en = false;
+		pr_cdr_beta_dac = BIT(3);
+		rx_rate_ctrl = BIT(1);
+		cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+		sigdet_vth_sel = BIT(1);
+		phyck_div = BIT(6) | BIT(1);
+		phyck_sel = BIT(1);
+		break;
+	default:
+		return;
+	}
+
+	/* Set RX rate ctrl */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_2,
+				   AIROHA_PCS_PMA_CK_RATE,
+				   AIROHA_PCS_PMA_CK_RATE_10);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+			   AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl));
+
+	/* Setup RX Path */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_5,
+			   AIROHA_PCS_PMA_FLL_IDAC_MIN |
+			   AIROHA_PCS_PMA_FLL_IDAC_MAX,
+			   FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ,
+			AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ |
+			AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB,
+			AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ);
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB,
+			AIROHA_PCS_ANA_FE_VCM_GEN_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+			AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_AEQ_CFORCE,
+			   AIROHA_PCS_ANA_AEQ_OFORCE,
+			   AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW,
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE,
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+			   AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+			  AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+			  AIROHA_PCS_PMA_DISB_LEQ);
+
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+			  AIROHA_PCS_ANA_CDR_PD_EDGE_DIS |
+			  AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
+			   AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+			AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+			   AIROHA_PCS_ANA_RX_DAC_MON |
+			   AIROHA_PCS_ANA_CDR_PR_XFICK_EN |
+			   AIROHA_PCS_ANA_CDR_PR_MONDPI_EN |
+			   AIROHA_PCS_ANA_CDR_PR_MONDPR_EN,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_MON, 0x0) |
+			   AIROHA_PCS_ANA_CDR_PR_XFICK_EN);
+
+	/* Setup FE Gain and FE Peacking */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL, 0x0));
+
+	/* Setup FE VOS */
+	if (interface != PHY_INTERFACE_MODE_USXGMII &&
+	    interface != PHY_INTERFACE_MODE_10GBASER)
+		regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+				   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+				   AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
+				   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+				   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
+
+	/* Setup FLL PR FMeter (no bypass mode)*/
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
+			   AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
+			   AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
+			   AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
+			   AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
+			   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
+
+	/* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
+	/* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
+	/* Setup REV */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_REV_0,
+			   AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL |
+			   AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL |
+			   AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK,
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) |
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) |
+			   FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0));
+
+	/* Setup Rdy Timeout */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+			   AIROHA_PCS_PMA_RX_RDY |
+			   AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+	/* Setup CaBoundry Init */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+			   AIROHA_PCS_PMA_RX_OS_START |
+			   AIROHA_PCS_PMA_OSC_SPEED_OPT,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
+			   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+			   AIROHA_PCS_PMA_RX_OS_END,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+			   AIROHA_PCS_PMA_RX_PICAL_END |
+			   AIROHA_PCS_PMA_RX_PICAL_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+			   AIROHA_PCS_PMA_RX_SDCAL_END |
+			   AIROHA_PCS_PMA_RX_SDCAL_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+			   AIROHA_PCS_PMA_RX_PDOS_END |
+			   AIROHA_PCS_PMA_RX_PDOS_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+			   AIROHA_PCS_PMA_RX_FEOS_END |
+			   AIROHA_PCS_PMA_RX_FEOS_START,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+	/* Setup By Serdes*/
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+			   AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+	/* Setup RX OSR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+			   AIROHA_PCS_ANA_CDR_PD_EDGE_DIS,
+			   osr ? AIROHA_PCS_ANA_CDR_PD_EDGE_DIS : 0);
+
+	/* Setup CDR LPF Ratio */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,
+			   AIROHA_PCS_ANA_CDR_LPF_TOP_LIM |
+			   AIROHA_PCS_ANA_CDR_LPF_RATIO,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x20000) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO, osr));
+
+	/* Setup CDR PR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC,
+			   AIROHA_PCS_ANA_CDR_PR_KBAND_DIV |
+			   AIROHA_PCS_ANA_CDR_PR_BETA_SEL |
+			   AIROHA_PCS_ANA_CDR_PR_VCOADC_OS |
+			   AIROHA_PCS_ANA_CDR_PR_BETA_DAC,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_KBAND_DIV, 0x4) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_SEL, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VCOADC_OS, 0x8) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC, pr_cdr_beta_dac));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,
+			   AIROHA_PCS_ANA_CDR_PR_FBKSEL |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL |
+			   AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL,
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND, pr_cdr_beta_dac) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x6) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x6));
+
+	/* Setup Eye Mon */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_3,
+			   AIROHA_PCS_PMA_EQ_DEBUG_SEL |
+			   AIROHA_PCS_PMA_FOM_NUM_ORDER |
+			   AIROHA_PCS_PMA_A_SEL,
+			   FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
+			   FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+			   FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+			   AIROHA_PCS_PMA_DATA_SHIFT |
+			   AIROHA_PCS_PMA_EYECNT_FAST,
+			   AIROHA_PCS_PMA_EYECNT_FAST);
+
+	/* Calibration Start */
+
+	/* Enable SYS */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+			   AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+			   FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+			AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+	usleep_range(500, 600);
+
+	/* Setup FLL PR FMeter (bypass mode)*/
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+			  AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+			AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+	/* Enable CMLEQ */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN,
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN |
+			   AIROHA_PCS_ANA_RX_FE_EQ_HZEN,
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+			   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN);
+
+	/* Setup CDR PR */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+			   AIROHA_PCS_ANA_CDR_PR_CAP_EN |
+			   AIROHA_PCS_ANA_CDR_BUF_IN_SR,
+			   (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) |
+			   FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr));
+
+	/* Setup CDR xxx Pwdb, set force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+			   AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+			  AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
+			  AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+			  AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+			  AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+	/* FIXME: Ask Airoha WHY it's cleared? */
+	/* regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+	 *		  AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
+	 */
+
+	/* Setup SigDet */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+			   AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL |
+			   AIROHA_PCS_ANA_RX_SIGDET_PEAK,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, sigdet_vth_sel) |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, BIT(1)));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE,
+			   AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL,
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, BIT(1) | BIT(0)));
+
+	/* Disable SigDet Pwdb */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+			  AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+	/* Setup PHYCK */
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,
+			   AIROHA_PCS_ANA_RX_TDC_CK_SEL |
+			   AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+			   AIROHA_PCS_ANA_RX_PHYCK_SEL |
+			   AIROHA_PCS_ANA_RX_PHYCK_DIV,
+			   AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel) |
+			   FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div));
+
+	regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL,
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE |
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL,
+			   AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE);
+
+	usleep_range(100, 200);
+
+	/* Enable CDR xxx Pwdb */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+			AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+			AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
+			AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+			AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+			AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+	/* Enable SigDet Pwdb */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+			AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+}
+
+static unsigned int airoha_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
+						 u32 cdr_pr_idac)
+{
+	u32 val;
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			   AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+			   FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+				      cdr_pr_idac));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+			   AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
+
+	usleep_range(5000, 7000);
+
+	regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+
+	return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
+}
+
+static void airoha_pcs_rx_prcal(struct airoha_pcs_priv *priv,
+				phy_interface_t interface)
+{
+	unsigned int remaining_prcal_search_bits;
+	unsigned int fl_out_diff = UINT_MAX;
+	u32 best_prcal_search_bit;
+	unsigned int prcal_search;
+	int prcal_search_bit;
+	unsigned int fl_out;
+	int cdr_pr_idac = 0;
+
+	u32 target_fl_out;
+	u32 cyclecnt;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:  /* DS_1.25G      / US_1.25G  */
+	case PHY_INTERFACE_MODE_1000BASEX:
+		target_fl_out = 0xa3d6;
+		cyclecnt = 32767;
+		break;
+	case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G   / US_9.95328G */
+		target_fl_out = 0xa000;
+		cyclecnt = 20000;
+		break;
+	case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G  / US_1.25G */
+	case PHY_INTERFACE_MODE_10GBASER:
+		target_fl_out = 0x9edf;
+		cyclecnt = 32767;
+		break;
+	default:
+		return;
+	}
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
+			   AIROHA_PCS_PMA_LOCK_TARGET_END |
+			   AIROHA_PCS_PMA_LOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+			   AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+			   AIROHA_PCS_PMA_LOCK_CYCLECNT,
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+			   AIROHA_PCS_PMA_LOCK_UNLOCKTH |
+			   AIROHA_PCS_PMA_LOCK_LOCKTH,
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
+			   FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
+			   AIROHA_PCS_PMA_UNLOCK_TARGET_END |
+			   AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
+			   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
+
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
+			AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	/* Calibration logic:
+	 * First check the major value by looping with every
+	 * value in the last 3 bit of CDR_PR_IDAC.
+	 * Get the signal level and save the value that is closer to
+	 * the target.
+	 *
+	 * Then check each remaining 7 bits in search of the deadline
+	 * where the signal gets farther than signal target.
+	 *
+	 * Finally fine tune for the remaining bits to find the one that
+	 * produce the closest signal level.
+	 */
+	for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		/* try to find the upper value by setting the last 3 bit */
+		cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+					     prcal_search);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		if (fl_out_diff_new < fl_out_diff) {
+			cdr_pr_idac = cdr_pr_idac_tmp;
+			fl_out_diff = fl_out_diff_new;
+		}
+	}
+
+	/* Deadline search part.
+	 * We start from top bits to bottom as we progressively decrease the
+	 * signal.
+	 */
+	for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		if (fl_out_diff_new < fl_out_diff) {
+			best_prcal_search_bit = prcal_search_bit;
+			fl_out_diff = fl_out_diff_new;
+		}
+	}
+
+	/* Set the idac with the best value we found and
+	 * reset the search bit to start from bottom to top.
+	 */
+	cdr_pr_idac |= BIT(best_prcal_search_bit);
+	remaining_prcal_search_bits = best_prcal_search_bit;
+	prcal_search_bit = 0;
+
+	/* Fine tune part.
+	 * Test remaining bits to find an even closer signal level to target
+	 * by increasing the signal.
+	 */
+	while (remaining_prcal_search_bits) {
+		unsigned int fl_out_diff_new;
+		u32 cdr_pr_idac_tmp;
+
+		cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+		fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+		/* Use absolute values to find the closest one to target */
+		fl_out_diff_new = abs(fl_out - target_fl_out);
+		/* Assume we found the deadline when the new absolue signal difference
+		 * from target is greater than the previous and the difference is at
+		 * least 10% greater between the old and new value.
+		 * This is to account for signal detection level tollerance making
+		 * sure we are actually over a deadline (AKA we are getting farther
+		 * from target)
+		 */
+		if (fl_out_diff_new > fl_out_diff &&
+		    (abs(fl_out_diff_new - fl_out_diff) * 100) / fl_out_diff > 10) {
+			/* Exit early if we are already at the deadline */
+			if (prcal_search_bit == 0)
+				break;
+
+			/* We found the deadline, set the value to the previous
+			 * bit, and reset the loop to fine tune with the
+			 * remaining values.
+			 */
+			cdr_pr_idac |= BIT(prcal_search_bit - 1);
+			remaining_prcal_search_bits = prcal_search_bit - 1;
+			prcal_search_bit = 0;
+		} else {
+			/* Update the signal level diff and try the next bit */
+			fl_out_diff = fl_out_diff_new;
+
+			/* If we didn't found the deadline, set the last bit
+			 * and reset the loop to fine tune with the remainig
+			 * values.
+			 */
+			if (prcal_search_bit == remaining_prcal_search_bits - 1) {
+				cdr_pr_idac |= BIT(prcal_search_bit);
+				remaining_prcal_search_bits = prcal_search_bit;
+				prcal_search_bit = 0;
+			} else {
+				prcal_search_bit++;
+			}
+		}
+	}
+
+	fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac);
+	dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
+	if (abs(fl_out - target_fl_out) > 100)
+		dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n",
+			abs(fl_out - target_fl_out), target_fl_out);
+
+	/* Setup Load Band */
+	regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
+			  AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
+
+	/* Disable force of LPF C previously enabled */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_B,
+			AIROHA_PCS_PMA_LOAD_EN);
+
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_1,
+			   AIROHA_PCS_PMA_LPATH_IDAC,
+			   FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			  AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+}
+
+/* This is used to both calibrate and lock to signal (after a previous
+ * calibration) after a global reset.
+ */
+static void airoha_pcs_cdr_reset(struct airoha_pcs_priv *priv,
+				 phy_interface_t interface, bool calibrate)
+{
+	/* Setup LPF L2D force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+	/* Calibrate IDAC and setup Load Band */
+	if (calibrate)
+		airoha_pcs_rx_prcal(priv, interface);
+
+	/* Setup LPF RSTB force and disable */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+			   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+			   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+	usleep_range(700, 1000);
+
+	/* Force Enable LPF RSTB */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+	usleep_range(100, 200);
+
+	/* Force Enable LPF L2D */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+	/* Disable LPF RSTB force bit */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+	/* Disable LPF L2D force bit */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+			  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+}
+
+static int airoha_pcs_phya_bringup(struct airoha_pcs_priv *priv,
+				   phy_interface_t interface)
+{
+	int calibration_try = 0;
+	u32 val;
+
+	airoha_pcs_tx_bringup(priv, interface);
+	airoha_pcs_rx_bringup(priv, interface);
+
+	usleep_range(100, 200);
+
+retry_calibration:
+	airoha_pcs_cdr_reset(priv, interface, true);
+
+	/* Global reset clear */
+	regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			   AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
+			   AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+			   AIROHA_PCS_PMA_SW_REF_RST_N |
+			   AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+			   AIROHA_PCS_PMA_SW_PMA_RST_N |
+			   AIROHA_PCS_PMA_SW_TX_RST_N |
+			   AIROHA_PCS_PMA_SW_RX_RST_N |
+			   AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
+			   AIROHA_PCS_PMA_SW_REF_RST_N);
+
+	usleep_range(100, 200);
+
+	/* Global reset */
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
+			AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+			AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+			AIROHA_PCS_PMA_SW_REF_RST_N |
+			AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+			AIROHA_PCS_PMA_SW_PMA_RST_N |
+			AIROHA_PCS_PMA_SW_TX_RST_N |
+			AIROHA_PCS_PMA_SW_RX_RST_N |
+			AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+	usleep_range(5000, 7000);
+
+	airoha_pcs_cdr_reset(priv, interface, false);
+
+	/* It was discovered that after a global reset and auto mode gets
+	 * actually enabled, the fl_out from calibration might change and
+	 * might deviates a lot from the expected value it was calibrated for.
+	 * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
+	 * (frequency level output) or no signal can correctly be transmitted.
+	 * This is detected by checking the FreqDet module Lock bit.
+	 *
+	 * If it's detected that the FreqDet module is not locked, retry
+	 * calibration. From observation on real hardware with a 10g SFP module,
+	 * it required a maximum of an additional calibration to actually make
+	 * the FreqDet module to lock. Try 10 times before failing to handle
+	 * really strange case.
+	 */
+	regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+	if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
+		if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
+			dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
+				AIROHA_PCS_MAX_CALIBRATION_TRY);
+			return -EIO;
+		}
+
+		calibration_try++;
+
+		dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
+		goto retry_calibration;
+	}
+
+	return 0;
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
+				       unsigned int neg_mode,
+				       struct phylink_link_state *state)
+{
+	u32 bmsr, lpa;
+
+	regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+		    &bmsr);
+	regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
+		    &lpa);
+
+	bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+		AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+		AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+		AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+	lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
+	phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv,
+					 struct phylink_link_state *state)
+{
+	u32 lpa;
+
+	/* Toggle AN Status */
+	regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+			AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+	regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+			  AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+	regmap_read(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
+
+	state->link = !!(lpa & MDIO_USXGMII_LINK);
+	state->an_complete = state->link;
+
+	phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
+				 unsigned int neg_mode,
+				 struct phylink_link_state *state)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	switch (state->interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		airoha_pcs_get_state_sgmii(priv, neg_mode, state);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10GBASER:
+		airoha_pcs_get_state_usxgmii(priv, state);
+		break;
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,
+				  phy_interface_t interface)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	/* MPI MBI disable */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			AIROHA_PCS_XFI_RXMPI_STOP |
+			AIROHA_PCS_XFI_RXMBI_STOP |
+			AIROHA_PCS_XFI_TXMPI_STOP |
+			AIROHA_PCS_XFI_TXMBI_STOP);
+
+	/* Write 1 to trigger reset and clear */
+	regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+			  AIROHA_PCS_XFI_MAC_LOGIC_RST);
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+			AIROHA_PCS_XFI_MAC_LOGIC_RST);
+
+	usleep_range(1000, 2000);
+
+	/* Clear XFI MAC counter */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,
+			AIROHA_PCS_XFI_GLB_CNT_CLR);
+}
+
+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+			     phy_interface_t interface,
+			     const unsigned long *advertising,
+			     bool permit_pause_to_mac)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+	u32 rate_adapt;
+	int ret;
+
+	priv->interface = interface;
+
+	/* Select HSGMII or USXGMII in SCU regs */
+	airoha_pcs_setup_scu(priv, interface);
+
+	/* Enable Analog Common Lane */
+	regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CMN_EN,
+			AIROHA_PCS_ANA_CMN_EN);
+
+	/* Setup PLL */
+	airoha_pcs_pll_bringup(priv, interface);
+
+	/* Setup PHYA */
+	ret = airoha_pcs_phya_bringup(priv, interface);
+	if (ret)
+		return ret;
+
+	/* Set final configuration for various modes */
+	airoha_pcs_init(priv, interface);
+
+	/* Configure Interrupt for various modes */
+	airoha_pcs_interrupt_init(priv, interface);
+
+	/* FIXME: With an attached Aeonsemi PHY, rate adaption is needed
+	 * even with no inband.
+	 */
+	rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+		     AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+
+	/* AN Auto Settings (Rate Adaptation) */
+	regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+			   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
+
+	/* FIXME: With an attached Aeonsemi PHY, AN is needed
+	 * even with no inband.
+	 */
+	if (interface == PHY_INTERFACE_MODE_USXGMII ||
+	    interface == PHY_INTERFACE_MODE_10GBASER) {
+		regmap_set_bits(priv->usxgmii_pcs,
+				AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				AIROHA_PCS_USXGMII_AN_ENABLE);
+	}
+
+	/* Clear any force bit that my be set by bootloader */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+				  AIROHA_PCS_LINK_MODE_P0 |
+				  AIROHA_PCS_FORCE_SPD_MODE_P0 |
+				  AIROHA_PCS_FORCE_LINKDOWN_P0 |
+				  AIROHA_PCS_FORCE_LINKUP_P0);
+	}
+
+	/* Toggle Rate Adaption for SGMII/HSGMII mode */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+			regmap_clear_bits(priv->hsgmii_rate_adp,
+					  AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+					  AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+		else
+			regmap_set_bits(priv->hsgmii_rate_adp,
+					AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+					AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+	}
+
+	/* Setup AN Link Timer */
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX) {
+		u32 an_timer;
+
+		an_timer = phylink_get_link_timer_ns(interface);
+
+		/* Value needs to be shifted by 4, seems value is internally * 16 */
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
+				   AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+					      an_timer >> 4));
+
+		regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
+				   AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+					      an_timer >> 4));
+	}
+
+	/* Setup SGMII AN and advertisement in DEV_ABILITY */
+	if (interface == PHY_INTERFACE_MODE_SGMII &&
+	    neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+									 advertising);
+		if (advertise < 0)
+			return advertise;
+
+		regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
+				   AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+				   FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+					      advertise));
+	} else {
+		regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				  AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+	}
+
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_1000BASEX) {
+		u32 if_mode = AIROHA_PCS_HSGMII_AN_SGMII_EN |
+			      AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
+
+		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+			regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+					AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+			/* Clear force speed bits and MAC mode */
+			regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+					  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+					  AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+					  AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
+					  AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+		} else {
+			if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
+
+			regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+					  AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+			/* AN off force rate adaption, speed is set later in Link Up */
+			regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					   AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT,
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+		}
+
+		regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+				   AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
+
+		/* FIXME: Airoha apply a different configuration here */
+		/* They force rate adaption */
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+				AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
+				AIROHA_PCS_HSGMII_PCS_MODE2_EN);
+	}
+
+	if (interface == PHY_INTERFACE_MODE_1000BASEX &&
+	    neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+				AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
+
+		regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
+				AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+	}
+
+	/* Configure Flow Control on XFI */
+	regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			   AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
+			   permit_pause_to_mac ?
+				AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
+				0);
+
+	return 0;
+}
+
+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	switch (priv->interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+		udelay(3);
+		regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+				  AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+		break;
+	case PHY_INTERFACE_MODE_USXGMII:
+		regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				AIROHA_PCS_USXGMII_AN_RESTART);
+		udelay(3);
+		regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+				  AIROHA_PCS_USXGMII_AN_RESTART);
+	default:
+		return;
+	}
+}
+
+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+			       phy_interface_t interface, int speed, int duplex)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		if (interface == PHY_INTERFACE_MODE_SGMII) {
+			regmap_update_bits(priv->hsgmii_rate_adp,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
+			udelay(1);
+			regmap_update_bits(priv->hsgmii_rate_adp,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+					   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
+					   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
+		}
+	} else {
+		if (interface == PHY_INTERFACE_MODE_USXGMII ||
+		    interface == PHY_INTERFACE_MODE_10GBASER) {
+			u32 mode;
+			u32 rate_adapt;
+
+			switch (speed) {
+			case SPEED_10000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
+				mode = AIROHA_PCS_USXGMII_MODE_10000;
+				break;
+			case SPEED_5000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
+				mode = AIROHA_PCS_USXGMII_MODE_5000;
+				break;
+			case SPEED_2500:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
+				mode = AIROHA_PCS_USXGMII_MODE_2500;
+				break;
+			case SPEED_1000:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
+				mode = AIROHA_PCS_USXGMII_MODE_1000;
+				break;
+			case SPEED_100:
+				rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
+				mode = AIROHA_PCS_USXGMII_MODE_100;
+				break;
+			}
+
+			/* Trigger USXGMII change mode and force selected speed */
+			regmap_update_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+					   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE |
+					   AIROHA_PCS_USXGMII_MODE,
+					   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | mode);
+
+			regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
+					   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+					   rate_adapt);
+		}
+
+		if (interface == PHY_INTERFACE_MODE_SGMII ||
+		    interface == PHY_INTERFACE_MODE_1000BASEX) {
+			u32 force_speed;
+			u32 rate_adapt;
+
+			switch (speed) {
+			case SPEED_1000:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
+				break;
+			case SPEED_100:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
+				break;
+			case SPEED_10:
+				force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
+				rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
+				break;
+			}
+
+			regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+					   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+					   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
+					   force_speed | rate_adapt);
+		}
+
+		if (interface == PHY_INTERFACE_MODE_SGMII ||
+		    interface == PHY_INTERFACE_MODE_2500BASEX) {
+			u32 ck_gen_mode;
+			u32 speed_reg;
+			u32 if_mode;
+
+			switch (speed) {
+			case SPEED_2500:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
+				break;
+			case SPEED_1000:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
+				break;
+			case SPEED_100:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
+				break;
+			case SPEED_10:
+				speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+				if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
+				ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
+				break;
+			}
+
+			if (interface == PHY_INTERFACE_MODE_SGMII) {
+				regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+						   AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
+						   if_mode);
+
+				regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
+						   ck_gen_mode |
+						   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
+			}
+
+			regmap_update_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+					   AIROHA_PCS_LINK_MODE_P0 |
+					   AIROHA_PCS_FORCE_SPD_MODE_P0,
+					   speed_reg |
+					   AIROHA_PCS_FORCE_SPD_MODE_P0);
+		}
+	}
+
+	/* Reset TXPCS on link up */
+	regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			  AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+	usleep_range(100, 200);
+
+	regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+			AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+	/* BPI BMI enable */
+	regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			  AIROHA_PCS_XFI_RXMPI_STOP |
+			  AIROHA_PCS_XFI_RXMBI_STOP |
+			  AIROHA_PCS_XFI_TXMPI_STOP |
+			  AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_link_down(struct phylink_pcs *pcs)
+{
+	struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+	/* MPI MBI disable */
+	regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+			AIROHA_PCS_XFI_RXMPI_STOP |
+			AIROHA_PCS_XFI_RXMBI_STOP |
+			AIROHA_PCS_XFI_TXMPI_STOP |
+			AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static const struct phylink_pcs_ops airoha_pcs_ops = {
+	.pcs_get_state = airoha_pcs_get_state,
+	.pcs_pre_config = airoha_pcs_pre_config,
+	.pcs_config = airoha_pcs_config,
+	.pcs_an_restart = airoha_pcs_an_restart,
+	.pcs_link_up = airoha_pcs_link_up,
+	.pcs_link_down = airoha_pcs_link_down,
+};
+
+static const struct regmap_config airoha_pcs_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+	struct regmap_config syscon_config = airoha_pcs_regmap_config;
+	struct device *dev = &pdev->dev;
+	struct airoha_pcs_priv *priv;
+	void __iomem *base;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	priv->data = of_device_get_match_data(dev);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_mac");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_mac";
+	priv->xfi_mac = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_mac))
+		return PTR_ERR(priv->xfi_mac);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_an");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_an";
+	priv->hsgmii_an = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_an))
+		return PTR_ERR(priv->hsgmii_an);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_pcs");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_pcs";
+	priv->hsgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_pcs))
+		return PTR_ERR(priv->hsgmii_pcs);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_rate_adp");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "hsgmii_rate_adp";
+	priv->hsgmii_rate_adp = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->hsgmii_rate_adp))
+		return PTR_ERR(priv->hsgmii_rate_adp);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "multi_sgmii");
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	syscon_config.name = "multi_sgmii";
+	priv->multi_sgmii = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->multi_sgmii))
+		return PTR_ERR(priv->multi_sgmii);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "usxgmii");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "usxgmii";
+	priv->usxgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->usxgmii_pcs))
+		return PTR_ERR(priv->usxgmii_pcs);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_pma");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_pma";
+	priv->xfi_pma = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_pma))
+		return PTR_ERR(priv->xfi_pma);
+
+	base = devm_platform_ioremap_resource_byname(pdev, "xfi_ana");
+	if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+		return PTR_ERR(base);
+
+	syscon_config.name = "xfi_ana";
+	priv->xfi_ana = devm_regmap_init_mmio(dev, base, &syscon_config);
+	if (IS_ERR(priv->xfi_ana))
+		return PTR_ERR(priv->xfi_ana);
+
+	/* SCU is used to toggle XFI or HSGMII in global SoC registers */
+	priv->scu = syscon_regmap_lookup_by_compatible("airoha,en7581-scu");
+	if (IS_ERR(priv->scu))
+		return PTR_ERR(priv->scu);
+
+	priv->rsts[0].id = "mac";
+	priv->rsts[1].id = "phy";
+	ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(priv->rsts),
+						    priv->rsts);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
+	platform_set_drvdata(pdev, priv);
+
+	priv->pcs.ops = &airoha_pcs_ops;
+	priv->pcs.poll = true;
+
+	__set_bit(PHY_INTERFACE_MODE_SGMII, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_1000BASEX, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_2500BASEX, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_10GBASER, priv->pcs.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_USXGMII, priv->pcs.supported_interfaces);
+
+	return fwnode_pcs_add_provider(dev_fwnode(dev), fwnode_pcs_simple_get,
+				   &priv->pcs);
+}
+
+static void airoha_pcs_remove(struct platform_device *pdev)
+{
+	struct airoha_pcs_priv *priv = platform_get_drvdata(pdev);
+
+	fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+	rtnl_lock();
+	phylink_release_pcs(&priv->pcs);
+	rtnl_unlock();
+}
+
+static const struct airoha_pcs_match_data an7581_pcs_eth = {
+	.port_type = AIROHA_PCS_ETH,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pon = {
+	.port_type = AIROHA_PCS_PON,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+	{ .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+	{ .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
+
+static struct platform_driver airoha_pcs_driver = {
+	.driver = {
+		.name	 = "airoha-pcs",
+		.of_match_table = airoha_pcs_of_table,
+	},
+	.probe = airoha_pcs_probe,
+	.remove = airoha_pcs_remove,
+};
+module_platform_driver(airoha_pcs_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Airoha PCS driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 10/11] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
                   ` (8 preceding siblings ...)
  2025-05-10 10:23 ` [net-next PATCH v3 09/11] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 10:23 ` [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4 Christian Marangi
  10 siblings, 0 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Document support for Airoha Ethernet PCS for AN7581 SoC.

Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
the various Serdes port supporting different Media Independent Interface
(10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).

This follow the new PCS provider with the use of #pcs-cells property.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 .../bindings/net/pcs/airoha,pcs.yaml          | 112 ++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml

diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 000000000000..8bcf7757c728
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+  - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+  Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+  the various Serdes port supporting different Media Independent Interface
+  (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+  compatible:
+    enum:
+      - airoha,an7581-pcs-eth
+      - airoha,an7581-pcs-pon
+
+  reg:
+    items:
+      - description: XFI MAC reg
+      - description: HSGMII AN reg
+      - description: HSGMII PCS reg
+      - description: MULTI SGMII reg
+      - description: USXGMII reg
+      - description: HSGMII rate adaption reg
+      - description: XFI Analog register
+      - description: XFI PMA (Physical Medium Attachment) register
+
+  reg-names:
+    items:
+      - const: xfi_mac
+      - const: hsgmii_an
+      - const: hsgmii_pcs
+      - const: multi_sgmii
+      - const: usxgmii
+      - const: hsgmii_rate_adp
+      - const: xfi_ana
+      - const: xfi_pma
+
+  resets:
+    items:
+      - description: MAC reset
+      - description: PHY reset
+
+  reset-names:
+    items:
+      - const: mac
+      - const: phy
+
+  "#pcs-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - resets
+  - reset-names
+  - "#pcs-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/airoha,en7581-reset.h>
+
+    pcs@1fa08000 {
+        compatible = "airoha,an7581-pcs-pon";
+        reg = <0x1fa08000 0x1000>,
+              <0x1fa80000 0x60>,
+              <0x1fa80a00 0x164>,
+              <0x1fa84000 0x450>,
+              <0x1fa85900 0x338>,
+              <0x1fa86000 0x300>,
+              <0x1fa8a000 0x1000>,
+              <0x1fa8b000 0x1000>;
+        reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+                    "multi_sgmii", "usxgmii",
+                    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+        resets = <&scuclk EN7581_XPON_MAC_RST>,
+                 <&scuclk EN7581_XPON_PHY_RST>;
+        reset-names = "mac", "phy";
+
+        #pcs-cells = <0>;
+    };
+
+    pcs@1fa09000 {
+        compatible = "airoha,an7581-pcs-eth";
+        reg = <0x1fa09000 0x1000>,
+              <0x1fa70000 0x60>,
+              <0x1fa70a00 0x164>,
+              <0x1fa74000 0x450>,
+              <0x1fa75900 0x338>,
+              <0x1fa76000 0x300>,
+              <0x1fa7a000 0x1000>,
+              <0x1fa7b000 0x1000>;
+        reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+                    "multi_sgmii", "usxgmii",
+                    "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+        resets = <&scuclk EN7581_XSI_MAC_RST>,
+                 <&scuclk EN7581_XSI_PHY_RST>;
+        reset-names = "mac", "phy";
+
+        #pcs-cells = <0>;
+    };
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4
  2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
                   ` (9 preceding siblings ...)
  2025-05-10 10:23 ` [net-next PATCH v3 10/11] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Christian Marangi
@ 2025-05-10 10:23 ` Christian Marangi
  2025-05-10 12:23   ` Lorenzo Bianconi
  2025-05-10 17:26   ` kernel test robot
  10 siblings, 2 replies; 14+ messages in thread
From: Christian Marangi @ 2025-05-10 10:23 UTC (permalink / raw)
  To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Lorenzo Bianconi, Heiner Kallweit, Russell King, Philipp Zabel,
	Christian Marangi, Daniel Golle, netdev, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek

Add phylink support for GDM2/3/4 port that require configuration of the
PCS to make the external PHY or attached SFP cage work.

These needs to be defined in the GDM port node using the pcs-handle
property.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/ethernet/airoha/airoha_eth.c  | 138 ++++++++++++++++++++++
 drivers/net/ethernet/airoha/airoha_eth.h  |   3 +
 drivers/net/ethernet/airoha/airoha_regs.h |  12 ++
 3 files changed, 153 insertions(+)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931f..17521be820b5 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -7,6 +7,7 @@
 #include <linux/of_net.h>
 #include <linux/platform_device.h>
 #include <linux/tcp.h>
+#include <linux/pcs/pcs.h>
 #include <linux/u64_stats_sync.h>
 #include <net/dst_metadata.h>
 #include <net/page_pool/helpers.h>
@@ -79,6 +80,11 @@ static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
 	return port->id == 1;
 }
 
+static bool airhoa_is_phy_external(struct airoha_gdm_port *port)
+{
+	return port->id != 1;
+}
+
 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
 {
 	struct airoha_eth *eth = port->qdma->eth;
@@ -1613,6 +1619,17 @@ static int airoha_dev_open(struct net_device *dev)
 	struct airoha_gdm_port *port = netdev_priv(dev);
 	struct airoha_qdma *qdma = port->qdma;
 
+	if (airhoa_is_phy_external(port)) {
+		err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);
+		if (err) {
+			netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
+				   err);
+			return err;
+		}
+
+		phylink_start(port->phylink);
+	}
+
 	netif_tx_start_all_queues(dev);
 	err = airoha_set_vip_for_gdm_port(port, true);
 	if (err)
@@ -1665,6 +1682,11 @@ static int airoha_dev_stop(struct net_device *dev)
 		}
 	}
 
+	if (airhoa_is_phy_external(port)) {
+		phylink_stop(port->phylink);
+		phylink_disconnect_phy(port->phylink);
+	}
+
 	return 0;
 }
 
@@ -2795,6 +2817,110 @@ bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
 	return false;
 }
 
+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
+			       unsigned int mode, phy_interface_t interface,
+			       int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+	struct airoha_gdm_port *port = container_of(config, struct airoha_gdm_port,
+						    phylink_config);
+	struct airoha_qdma *qdma = port->qdma;
+	struct airoha_eth *eth = qdma->eth;
+	u32 frag_size_tx, frag_size_rx;
+
+	switch (speed) {
+	case SPEED_10000:
+	case SPEED_5000:
+		frag_size_tx = 8;
+		frag_size_rx = 8;
+		break;
+	case SPEED_2500:
+		frag_size_tx = 2;
+		frag_size_rx = 1;
+		break;
+	default:
+		frag_size_tx = 1;
+		frag_size_rx = 0;
+	}
+
+	/* Configure TX/RX frag based on speed */
+	if (port->id == 4) {
+		airoha_fe_rmw(eth, REG_GDMA4_TMBI_FRAG, GDMA4_SGMII0_TX_FRAG_SIZE,
+			      FIELD_PREP(GDMA4_SGMII0_TX_FRAG_SIZE, frag_size_tx));
+
+		airoha_fe_rmw(eth, REG_GDMA4_RMBI_FRAG, GDMA4_SGMII0_RX_FRAG_SIZE,
+			      FIELD_PREP(GDMA4_SGMII0_RX_FRAG_SIZE, frag_size_rx));
+	}
+}
+
+static const struct phylink_mac_ops airoha_phylink_ops = {
+	.mac_link_up = airoha_mac_link_up,
+};
+
+static int airoha_setup_phylink(struct net_device *dev)
+{
+	struct airoha_gdm_port *port = netdev_priv(dev);
+	struct device_node *np = dev->dev.of_node;
+	struct phylink_pcs **available_pcs;
+	phy_interface_t phy_mode;
+	struct phylink *phylink;
+	unsigned int num_pcs;
+	int err;
+
+	err = of_get_phy_mode(np, &phy_mode);
+	if (err) {
+		dev_err(&dev->dev, "incorrect phy-mode\n");
+		return err;
+	}
+
+	port->phylink_config.dev = &dev->dev;
+	port->phylink_config.type = PHYLINK_NETDEV;
+	port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+						MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD |
+						MAC_5000FD | MAC_10000FD;
+
+	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), NULL, &num_pcs);
+	if (err)
+		return err;
+
+	available_pcs = kcalloc(num_pcs, sizeof(*available_pcs), GFP_KERNEL);
+	if (!available_pcs)
+		return -ENOMEM;
+
+	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
+				       &num_pcs);
+	if (err)
+		goto out;
+
+	port->phylink_config.available_pcs = available_pcs;
+	port->phylink_config.num_available_pcs = num_pcs;
+
+	__set_bit(PHY_INTERFACE_MODE_SGMII,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
+		  port->phylink_config.supported_interfaces);
+	__set_bit(PHY_INTERFACE_MODE_USXGMII,
+		  port->phylink_config.supported_interfaces);
+
+	phy_interface_copy(port->phylink_config.pcs_interfaces,
+			   port->phylink_config.supported_interfaces);
+
+	phylink = phylink_create(&port->phylink_config,
+				 of_fwnode_handle(np),
+				 phy_mode, &airoha_phylink_ops);
+	if (IS_ERR(phylink)) {
+		err = PTR_ERR(phylink);
+		goto out;
+	}
+
+	port->phylink = phylink;
+out:
+	kfree(available_pcs);
+
+	return err;
+}
+
 static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 				 struct device_node *np, int index)
 {
@@ -2873,6 +2999,12 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
 	if (err)
 		return err;
 
+	if (airhoa_is_phy_external(port)) {
+		err = airoha_setup_phylink(dev);
+		if (err)
+			return err;
+	}
+
 	return register_netdev(dev);
 }
 
@@ -2967,6 +3099,9 @@ static int airoha_probe(struct platform_device *pdev)
 		struct airoha_gdm_port *port = eth->ports[i];
 
 		if (port && port->dev->reg_state == NETREG_REGISTERED) {
+			if (airhoa_is_phy_external(port))
+				phylink_destroy(port->phylink);
+
 			unregister_netdev(port->dev);
 			airoha_metadata_dst_free(port);
 		}
@@ -2994,6 +3129,9 @@ static void airoha_remove(struct platform_device *pdev)
 			continue;
 
 		airoha_dev_stop(port->dev);
+		if (airhoa_is_phy_external(port))
+			phylink_destroy(port->phylink);
+
 		unregister_netdev(port->dev);
 		airoha_metadata_dst_free(port);
 	}
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 53f39083a8b0..73a500474076 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -498,6 +498,9 @@ struct airoha_gdm_port {
 	struct net_device *dev;
 	int id;
 
+	struct phylink *phylink;
+	struct phylink_config phylink_config;
+
 	struct airoha_hw_stats stats;
 
 	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index d931530fc96f..71c63108f0a8 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -357,6 +357,18 @@
 #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
 #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
 
+#define REG_GDMA4_TMBI_FRAG		0x2028
+#define GDMA4_SGMII1_TX_WEIGHT		GENMASK(31, 26)
+#define GDMA4_SGMII1_TX_FRAG_SIZE	GENMASK(25, 16)
+#define GDMA4_SGMII0_TX_WEIGHT		GENMASK(15, 10)
+#define GDMA4_SGMII0_TX_FRAG_SIZE	GENMASK(9, 0)
+
+#define REG_GDMA4_RMBI_FRAG		0x202c
+#define GDMA4_SGMII1_RX_WEIGHT		GENMASK(31, 26)
+#define GDMA4_SGMII1_RX_FRAG_SIZE	GENMASK(25, 16)
+#define GDMA4_SGMII0_RX_WEIGHT		GENMASK(15, 10)
+#define GDMA4_SGMII0_RX_FRAG_SIZE	GENMASK(9, 0)
+
 #define REG_MC_VLAN_EN			0x2100
 #define MC_VLAN_EN_MASK			BIT(0)
 
-- 
2.48.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* Re: [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4
  2025-05-10 10:23 ` [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4 Christian Marangi
@ 2025-05-10 12:23   ` Lorenzo Bianconi
  2025-05-10 17:26   ` kernel test robot
  1 sibling, 0 replies; 14+ messages in thread
From: Lorenzo Bianconi @ 2025-05-10 12:23 UTC (permalink / raw)
  To: Christian Marangi
  Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Heiner Kallweit, Russell King, Philipp Zabel, Daniel Golle,
	netdev, devicetree, linux-kernel, linux-arm-kernel,
	linux-mediatek

[-- Attachment #1: Type: text/plain, Size: 8834 bytes --]

> Add phylink support for GDM2/3/4 port that require configuration of the
> PCS to make the external PHY or attached SFP cage work.
> 
> These needs to be defined in the GDM port node using the pcs-handle
> property.

Hi Christian,

thx for the patch. Some comments inline.

Regards,
Lorenzo

> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c  | 138 ++++++++++++++++++++++
>  drivers/net/ethernet/airoha/airoha_eth.h  |   3 +
>  drivers/net/ethernet/airoha/airoha_regs.h |  12 ++
>  3 files changed, 153 insertions(+)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 16c7896f931f..17521be820b5 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -7,6 +7,7 @@
>  #include <linux/of_net.h>
>  #include <linux/platform_device.h>
>  #include <linux/tcp.h>
> +#include <linux/pcs/pcs.h>
>  #include <linux/u64_stats_sync.h>
>  #include <net/dst_metadata.h>
>  #include <net/page_pool/helpers.h>
> @@ -79,6 +80,11 @@ static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
>  	return port->id == 1;
>  }
>  
> +static bool airhoa_is_phy_external(struct airoha_gdm_port *port)
> +{
> +	return port->id != 1;
> +}
> +
>  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
>  {
>  	struct airoha_eth *eth = port->qdma->eth;
> @@ -1613,6 +1619,17 @@ static int airoha_dev_open(struct net_device *dev)
>  	struct airoha_gdm_port *port = netdev_priv(dev);
>  	struct airoha_qdma *qdma = port->qdma;
>  
> +	if (airhoa_is_phy_external(port)) {
> +		err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);
> +		if (err) {
> +			netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
> +				   err);
> +			return err;
> +		}
> +
> +		phylink_start(port->phylink);
> +	}
> +
>  	netif_tx_start_all_queues(dev);
>  	err = airoha_set_vip_for_gdm_port(port, true);
>  	if (err)
> @@ -1665,6 +1682,11 @@ static int airoha_dev_stop(struct net_device *dev)
>  		}
>  	}
>  
> +	if (airhoa_is_phy_external(port)) {
> +		phylink_stop(port->phylink);
> +		phylink_disconnect_phy(port->phylink);
> +	}
> +
>  	return 0;
>  }
>  
> @@ -2795,6 +2817,110 @@ bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
>  	return false;
>  }
>  
> +static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
> +			       unsigned int mode, phy_interface_t interface,
> +			       int speed, int duplex, bool tx_pause, bool rx_pause)
> +{
> +	struct airoha_gdm_port *port = container_of(config, struct airoha_gdm_port,
> +						    phylink_config);
> +	struct airoha_qdma *qdma = port->qdma;
> +	struct airoha_eth *eth = qdma->eth;
> +	u32 frag_size_tx, frag_size_rx;

I guess we can just return here if port->id != 4 and avoid setting
frag_size_tx/frag_size_rx

> +
> +	switch (speed) {
> +	case SPEED_10000:
> +	case SPEED_5000:
> +		frag_size_tx = 8;
> +		frag_size_rx = 8;
> +		break;
> +	case SPEED_2500:
> +		frag_size_tx = 2;
> +		frag_size_rx = 1;
> +		break;
> +	default:
> +		frag_size_tx = 1;
> +		frag_size_rx = 0;
> +	}
> +
> +	/* Configure TX/RX frag based on speed */
> +	if (port->id == 4) {
> +		airoha_fe_rmw(eth, REG_GDMA4_TMBI_FRAG, GDMA4_SGMII0_TX_FRAG_SIZE,
> +			      FIELD_PREP(GDMA4_SGMII0_TX_FRAG_SIZE, frag_size_tx));
> +
> +		airoha_fe_rmw(eth, REG_GDMA4_RMBI_FRAG, GDMA4_SGMII0_RX_FRAG_SIZE,
> +			      FIELD_PREP(GDMA4_SGMII0_RX_FRAG_SIZE, frag_size_rx));
> +	}
> +}
> +
> +static const struct phylink_mac_ops airoha_phylink_ops = {
> +	.mac_link_up = airoha_mac_link_up,
> +};
> +
> +static int airoha_setup_phylink(struct net_device *dev)
> +{
> +	struct airoha_gdm_port *port = netdev_priv(dev);
> +	struct device_node *np = dev->dev.of_node;
> +	struct phylink_pcs **available_pcs;
> +	phy_interface_t phy_mode;
> +	struct phylink *phylink;
> +	unsigned int num_pcs;
> +	int err;
> +
> +	err = of_get_phy_mode(np, &phy_mode);
> +	if (err) {
> +		dev_err(&dev->dev, "incorrect phy-mode\n");
> +		return err;
> +	}
> +
> +	port->phylink_config.dev = &dev->dev;
> +	port->phylink_config.type = PHYLINK_NETDEV;
> +	port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> +						MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD |
> +						MAC_5000FD | MAC_10000FD;
> +
> +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), NULL, &num_pcs);
> +	if (err)
> +		return err;
> +
> +	available_pcs = kcalloc(num_pcs, sizeof(*available_pcs), GFP_KERNEL);
> +	if (!available_pcs)
> +		return -ENOMEM;

since airoha_setup_phylink() is just run in the following path:

airoha_probe() -> airoha_alloc_gdm_port()

we can use devm_kcalloc() and get rid of the kfree and the end of the routine.

> +
> +	err = fwnode_phylink_pcs_parse(dev_fwnode(&dev->dev), available_pcs,
> +				       &num_pcs);
> +	if (err)
> +		goto out;
> +
> +	port->phylink_config.available_pcs = available_pcs;
> +	port->phylink_config.num_available_pcs = num_pcs;
> +
> +	__set_bit(PHY_INTERFACE_MODE_SGMII,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
> +		  port->phylink_config.supported_interfaces);
> +	__set_bit(PHY_INTERFACE_MODE_USXGMII,
> +		  port->phylink_config.supported_interfaces);
> +
> +	phy_interface_copy(port->phylink_config.pcs_interfaces,
> +			   port->phylink_config.supported_interfaces);
> +
> +	phylink = phylink_create(&port->phylink_config,
> +				 of_fwnode_handle(np),
> +				 phy_mode, &airoha_phylink_ops);
> +	if (IS_ERR(phylink)) {
> +		err = PTR_ERR(phylink);
> +		goto out;
> +	}
> +
> +	port->phylink = phylink;
> +out:
> +	kfree(available_pcs);
> +
> +	return err;
> +}
> +
>  static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  				 struct device_node *np, int index)
>  {
> @@ -2873,6 +2999,12 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
>  	if (err)
>  		return err;
>  
> +	if (airhoa_is_phy_external(port)) {
> +		err = airoha_setup_phylink(dev);
> +		if (err)
> +			return err;
> +	}
> +
>  	return register_netdev(dev);

we should run phylink_destroy() if register_netdev() fails. Please take a
look to:

https://lore.kernel.org/netdev/aB8MPkMYXWvoaA03@lore-desk/T/#m0a036b0759384a38d2518025db46306858b5707b

>  }
>  
> @@ -2967,6 +3099,9 @@ static int airoha_probe(struct platform_device *pdev)
>  		struct airoha_gdm_port *port = eth->ports[i];
>  
>  		if (port && port->dev->reg_state == NETREG_REGISTERED) {
> +			if (airhoa_is_phy_external(port))
> +				phylink_destroy(port->phylink);
> +
>  			unregister_netdev(port->dev);
>  			airoha_metadata_dst_free(port);
>  		}
> @@ -2994,6 +3129,9 @@ static void airoha_remove(struct platform_device *pdev)
>  			continue;
>  
>  		airoha_dev_stop(port->dev);
> +		if (airhoa_is_phy_external(port))
> +			phylink_destroy(port->phylink);
> +
>  		unregister_netdev(port->dev);
>  		airoha_metadata_dst_free(port);
>  	}
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 53f39083a8b0..73a500474076 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -498,6 +498,9 @@ struct airoha_gdm_port {
>  	struct net_device *dev;
>  	int id;
>  
> +	struct phylink *phylink;
> +	struct phylink_config phylink_config;
> +
>  	struct airoha_hw_stats stats;
>  
>  	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
> diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
> index d931530fc96f..71c63108f0a8 100644
> --- a/drivers/net/ethernet/airoha/airoha_regs.h
> +++ b/drivers/net/ethernet/airoha/airoha_regs.h
> @@ -357,6 +357,18 @@
>  #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
>  #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
>  
> +#define REG_GDMA4_TMBI_FRAG		0x2028
> +#define GDMA4_SGMII1_TX_WEIGHT		GENMASK(31, 26)
> +#define GDMA4_SGMII1_TX_FRAG_SIZE	GENMASK(25, 16)
> +#define GDMA4_SGMII0_TX_WEIGHT		GENMASK(15, 10)
> +#define GDMA4_SGMII0_TX_FRAG_SIZE	GENMASK(9, 0)

in order to be consistent with the codebase, can you please add _MASK suffix
here?

> +
> +#define REG_GDMA4_RMBI_FRAG		0x202c
> +#define GDMA4_SGMII1_RX_WEIGHT		GENMASK(31, 26)
> +#define GDMA4_SGMII1_RX_FRAG_SIZE	GENMASK(25, 16)
> +#define GDMA4_SGMII0_RX_WEIGHT		GENMASK(15, 10)
> +#define GDMA4_SGMII0_RX_FRAG_SIZE	GENMASK(9, 0)
> +
>  #define REG_MC_VLAN_EN			0x2100
>  #define MC_VLAN_EN_MASK			BIT(0)
>  
> -- 
> 2.48.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4
  2025-05-10 10:23 ` [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4 Christian Marangi
  2025-05-10 12:23   ` Lorenzo Bianconi
@ 2025-05-10 17:26   ` kernel test robot
  1 sibling, 0 replies; 14+ messages in thread
From: kernel test robot @ 2025-05-10 17:26 UTC (permalink / raw)
  To: Christian Marangi, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Lorenzo Bianconi, Heiner Kallweit, Russell King,
	Philipp Zabel, Daniel Golle, devicetree, linux-kernel,
	linux-arm-kernel, linux-mediatek
  Cc: oe-kbuild-all, netdev

Hi Christian,

kernel test robot noticed the following build warnings:

[auto build test WARNING on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/Christian-Marangi/net-phylink-keep-and-use-MAC-supported_interfaces-in-phylink-struct/20250510-182833
base:   net-next/main
patch link:    https://lore.kernel.org/r/20250510102348.14134-12-ansuelsmth%40gmail.com
patch subject: [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4
config: sh-randconfig-002-20250510 (https://download.01.org/0day-ci/archive/20250511/202505110156.WGym4cxS-lkp@intel.com/config)
compiler: sh4-linux-gcc (GCC) 11.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250511/202505110156.WGym4cxS-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505110156.WGym4cxS-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/net/ethernet/airoha/airoha_eth.c:10:
>> include/linux/pcs/pcs.h:90:1: warning: 'fwnode_phylink_pcs_get_from_fwnode' defined but not used [-Wunused-function]
      90 | fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
         | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/pcs/pcs.h:78:12: warning: 'register_fwnode_pcs_notifier' defined but not used [-Wunused-function]
      78 | static int register_fwnode_pcs_notifier(struct notifier_block *nb)
         |            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/fwnode_phylink_pcs_get_from_fwnode +90 include/linux/pcs/pcs.h

91110a42083f1a Christian Marangi 2025-05-10  24  
90fbe52edd2a1f Christian Marangi 2025-05-10  25  /**
90fbe52edd2a1f Christian Marangi 2025-05-10  26   * fwnode_pcs_get - Retrieves a PCS from a firmware node
90fbe52edd2a1f Christian Marangi 2025-05-10  27   * @fwnode: firmware node
90fbe52edd2a1f Christian Marangi 2025-05-10  28   * @index: index fwnode PCS handle in firmware node
90fbe52edd2a1f Christian Marangi 2025-05-10  29   *
90fbe52edd2a1f Christian Marangi 2025-05-10  30   * Get a PCS from the firmware node at index.
90fbe52edd2a1f Christian Marangi 2025-05-10  31   *
90fbe52edd2a1f Christian Marangi 2025-05-10  32   * Returns a pointer to the phylink_pcs or a negative
90fbe52edd2a1f Christian Marangi 2025-05-10  33   * error pointer. Can return -EPROBE_DEFER if the PCS is not
90fbe52edd2a1f Christian Marangi 2025-05-10  34   * present in global providers list (either due to driver
90fbe52edd2a1f Christian Marangi 2025-05-10  35   * still needs to be probed or it failed to probe/removed)
90fbe52edd2a1f Christian Marangi 2025-05-10  36   */
90fbe52edd2a1f Christian Marangi 2025-05-10  37  struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
90fbe52edd2a1f Christian Marangi 2025-05-10  38  				   int index);
90fbe52edd2a1f Christian Marangi 2025-05-10  39  
91110a42083f1a Christian Marangi 2025-05-10  40  /**
91110a42083f1a Christian Marangi 2025-05-10  41   * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
91110a42083f1a Christian Marangi 2025-05-10  42   *					by the firmware node from a
91110a42083f1a Christian Marangi 2025-05-10  43   *					firmware node
91110a42083f1a Christian Marangi 2025-05-10  44   * @fwnode: firmware node
91110a42083f1a Christian Marangi 2025-05-10  45   * @pcs_fwnode: PCS firmware node
91110a42083f1a Christian Marangi 2025-05-10  46   *
91110a42083f1a Christian Marangi 2025-05-10  47   * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
91110a42083f1a Christian Marangi 2025-05-10  48   * 'pcs_fwnode' firmware node.
91110a42083f1a Christian Marangi 2025-05-10  49   *
91110a42083f1a Christian Marangi 2025-05-10  50   * Returns a pointer to the phylink_pcs or a negative
91110a42083f1a Christian Marangi 2025-05-10  51   * error pointer. Can return -EPROBE_DEFER if the PCS is not
91110a42083f1a Christian Marangi 2025-05-10  52   * present in global providers list (either due to driver
91110a42083f1a Christian Marangi 2025-05-10  53   * still needs to be probed or it failed to probe/removed)
91110a42083f1a Christian Marangi 2025-05-10  54   */
91110a42083f1a Christian Marangi 2025-05-10  55  struct phylink_pcs *
91110a42083f1a Christian Marangi 2025-05-10  56  fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
91110a42083f1a Christian Marangi 2025-05-10  57  				   struct fwnode_handle *pcs_fwnode);
91110a42083f1a Christian Marangi 2025-05-10  58  
90fbe52edd2a1f Christian Marangi 2025-05-10  59  /**
90fbe52edd2a1f Christian Marangi 2025-05-10  60   * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
90fbe52edd2a1f Christian Marangi 2025-05-10  61   * @fwnode: firmware node
90fbe52edd2a1f Christian Marangi 2025-05-10  62   * @available_pcs: pointer to preallocated array of PCS
90fbe52edd2a1f Christian Marangi 2025-05-10  63   * @num_pcs: where to store count of parsed PCS
90fbe52edd2a1f Christian Marangi 2025-05-10  64   *
90fbe52edd2a1f Christian Marangi 2025-05-10  65   * Generic helper function to fill available_pcs array with PCS parsed
90fbe52edd2a1f Christian Marangi 2025-05-10  66   * from a "pcs-handle" fwnode property defined in firmware node up to
90fbe52edd2a1f Christian Marangi 2025-05-10  67   * passed num_pcs.
90fbe52edd2a1f Christian Marangi 2025-05-10  68   *
90fbe52edd2a1f Christian Marangi 2025-05-10  69   * If available_pcs is NULL, num_pcs is updated with the count of the
90fbe52edd2a1f Christian Marangi 2025-05-10  70   * parsed PCS.
90fbe52edd2a1f Christian Marangi 2025-05-10  71   *
90fbe52edd2a1f Christian Marangi 2025-05-10  72   * Returns 0 or a negative error.
90fbe52edd2a1f Christian Marangi 2025-05-10  73   */
90fbe52edd2a1f Christian Marangi 2025-05-10  74  int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
90fbe52edd2a1f Christian Marangi 2025-05-10  75  			     struct phylink_pcs **available_pcs,
90fbe52edd2a1f Christian Marangi 2025-05-10  76  			     unsigned int *num_pcs);
90fbe52edd2a1f Christian Marangi 2025-05-10  77  #else
91110a42083f1a Christian Marangi 2025-05-10 @78  static int register_fwnode_pcs_notifier(struct notifier_block *nb)
91110a42083f1a Christian Marangi 2025-05-10  79  {
91110a42083f1a Christian Marangi 2025-05-10  80  	return -EOPNOTSUPP;
91110a42083f1a Christian Marangi 2025-05-10  81  }
91110a42083f1a Christian Marangi 2025-05-10  82  
90fbe52edd2a1f Christian Marangi 2025-05-10  83  static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
90fbe52edd2a1f Christian Marangi 2025-05-10  84  						 int index)
90fbe52edd2a1f Christian Marangi 2025-05-10  85  {
90fbe52edd2a1f Christian Marangi 2025-05-10  86  	return ERR_PTR(-ENOENT);
90fbe52edd2a1f Christian Marangi 2025-05-10  87  }
90fbe52edd2a1f Christian Marangi 2025-05-10  88  
91110a42083f1a Christian Marangi 2025-05-10  89  static struct phylink_pcs *
91110a42083f1a Christian Marangi 2025-05-10 @90  fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
91110a42083f1a Christian Marangi 2025-05-10  91  				   struct fwnode_handle *pcs_fwnode)
91110a42083f1a Christian Marangi 2025-05-10  92  {
91110a42083f1a Christian Marangi 2025-05-10  93  	return ERR_PTR(-ENOENT);
91110a42083f1a Christian Marangi 2025-05-10  94  }
91110a42083f1a Christian Marangi 2025-05-10  95  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2025-05-10 17:27 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-10 10:23 [net-next PATCH v3 00/11] net: pcs: Introduce support for fwnode PCS Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 01/11] net: phylink: keep and use MAC supported_interfaces in phylink struct Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 02/11] net: phy: introduce phy_interface_copy helper Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 03/11] net: phylink: introduce internal phylink PCS handling Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 04/11] net: phylink: add phylink_release_pcs() to externally release a PCS Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 05/11] net: pcs: implement Firmware node support for PCS driver Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 06/11] net: phylink: support late PCS provider attach Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 07/11] dt-bindings: net: ethernet-controller: permit to define multiple PCS Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 08/11] net: phylink: add .pcs_link_down PCS OP Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 09/11] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 10/11] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Christian Marangi
2025-05-10 10:23 ` [net-next PATCH v3 11/11] net: airoha: add phylink support for GDM2/3/4 Christian Marangi
2025-05-10 12:23   ` Lorenzo Bianconi
2025-05-10 17:26   ` kernel test robot

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).