Re: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Conor Dooley <conor@kernel.org>]

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On Mon, May 12, 2025 at 11:01:26AM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
> 
> On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@kernel.org> wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > When the binding was originally written, it was assumed that all
> > ax45mp-caches had the same properties etc. This has turned out to be
> > incorrect, as the QiLai SoC has a different number of cache-sets.
> >
> > Add a specific compatible for the RZ/Five for property enforcement and
> > in case there turns out to be additional differences between these
> > implementations of the cache controller.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > @@ -28,6 +28,7 @@ select:
> >  properties:
> >    compatible:
> >      items:
> > +      - const: renesas,r9a07g043f-cache
> 
> This name looks a bit too generic to me, as this is not a generic
> cache on the R9A07G043F SoC, but specific to the CPU cores.

So "reneasas,r9...-cpu-cache"?

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