[PATCH v1 0/2] Add specific RZ/Five cache compatible

[PATCH v1 0/2] Add specific RZ/Five cache compatible

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

I opted not to add fixes tags, but I can create them if you (Prabhakar
or Geert etc) think that I should.

CC: Ben Zong-You Xie <ben717@andestech.com>
CC: Conor Dooley <conor@kernel.org>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: Geert Uytterhoeven <geert+renesas@glider.be>
CC: Magnus Damm <magnus.damm@gmail.com>
CC: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-renesas-soc@vger.kernel.org
CC: linux-riscv@lists.infradead.org

Conor Dooley (2):
  dt-bindings: cache: add specific RZ/Five compatible to ax45mp
  riscv: dts: renesas: add specific RZ/Five cache compatible

 .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml      | 3 ++-
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi                    | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

-- 
2.45.2

[PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml      | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index d2cbe49f4e15f..f533bd178a9f6 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -28,6 +28,7 @@ select:
 properties:
   compatible:
     items:
+      - const: renesas,r9a07g043f-cache
       - const: andestech,ax45mp-cache
       - const: cache
 
@@ -70,7 +71,7 @@ examples:
     #include <dt-bindings/interrupt-controller/irq.h>
 
     cache-controller@13400000 {
-        compatible = "andestech,ax45mp-cache", "cache";
+        compatible = "renesas,r9a07g043f-cache", "andestech,ax45mp-cache", "cache";
         reg = <0x13400000 0x100000>;
         interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
         cache-line-size = <64>;
-- 
2.45.2

[PATCH v1 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index e0ddf8f602c79..66c6fe0cd162f 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -143,7 +143,7 @@ plic: interrupt-controller@12c00000 {
 	};
 
 	l2cache: cache-controller@13400000 {
-		compatible = "andestech,ax45mp-cache", "cache";
+		compatible = "renesas,r9a07g043f-cache", "andestech,ax45mp-cache", "cache";
 		reg = <0x0 0x13400000 0x0 0x100000>;
 		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
 		cache-size = <0x40000>;
-- 
2.45.2

Re: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Ben Zong-You Xie]

On Fri, May 09, 2025 at 04:37:57PM +0100, Conor Dooley wrote:
> [EXTERNAL MAIL]
> 
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
> 
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Acked-by: Ben Zong-You Xie <ben717@andestech.com>

Re: [PATCH v1 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

[Ben Zong-You Xie]

On Fri, May 09, 2025 at 04:37:59PM +0100, Conor Dooley wrote:
> [EXTERNAL MAIL]
> 
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
> 
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Acked-by: Ben Zong-You Xie <ben717@andestech.com>

Re: [PATCH v1 0/2] Add specific RZ/Five cache compatible

[Geert Uytterhoeven]

Hi Conor,

On Fri, 9 May 2025 at 17:38, Conor Dooley <conor@kernel.org> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> I opted not to add fixes tags, but I can create them if you (Prabhakar
> or Geert etc) think that I should.

It depends ;-)

Do you see a need for matching on the new compatible value in the
near future?
Is it OK to postpone the DTS patch to v6.17, or do you want to
fast-track it as a fix? I just sent my last normal PR for v6.16 on
Friday, before this series came in.

Thanks!

> Conor Dooley (2):
>   dt-bindings: cache: add specific RZ/Five compatible to ax45mp
>   riscv: dts: renesas: add specific RZ/Five cache compatible

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Geert Uytterhoeven]

Hi Conor,

On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@kernel.org> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> @@ -28,6 +28,7 @@ select:
>  properties:
>    compatible:
>      items:
> +      - const: renesas,r9a07g043f-cache

This name looks a bit too generic to me, as this is not a generic
cache on the R9A07G043F SoC, but specific to the CPU cores.

>        - const: andestech,ax45mp-cache
>        - const: cache
>
> @@ -70,7 +71,7 @@ examples:
>      #include <dt-bindings/interrupt-controller/irq.h>
>
>      cache-controller@13400000 {
> -        compatible = "andestech,ax45mp-cache", "cache";
> +        compatible = "renesas,r9a07g043f-cache", "andestech,ax45mp-cache", "cache";
>          reg = <0x13400000 0x100000>;
>          interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
>          cache-line-size = <64>;

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1190 bytes --]

On Mon, May 12, 2025 at 11:01:26AM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
> 
> On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@kernel.org> wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > When the binding was originally written, it was assumed that all
> > ax45mp-caches had the same properties etc. This has turned out to be
> > incorrect, as the QiLai SoC has a different number of cache-sets.
> >
> > Add a specific compatible for the RZ/Five for property enforcement and
> > in case there turns out to be additional differences between these
> > implementations of the cache controller.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > @@ -28,6 +28,7 @@ select:
> >  properties:
> >    compatible:
> >      items:
> > +      - const: renesas,r9a07g043f-cache
> 
> This name looks a bit too generic to me, as this is not a generic
> cache on the R9A07G043F SoC, but specific to the CPU cores.

So "reneasas,r9...-cpu-cache"?

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Re: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Lad, Prabhakar]

Hi Conor and Geert,

On Mon, May 12, 2025 at 10:59 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Mon, May 12, 2025 at 11:01:26AM +0200, Geert Uytterhoeven wrote:
> > Hi Conor,
> >
> > On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@kernel.org> wrote:
> > > From: Conor Dooley <conor.dooley@microchip.com>
> > >
> > > When the binding was originally written, it was assumed that all
> > > ax45mp-caches had the same properties etc. This has turned out to be
> > > incorrect, as the QiLai SoC has a different number of cache-sets.
> > >
> > > Add a specific compatible for the RZ/Five for property enforcement and
> > > in case there turns out to be additional differences between these
> > > implementations of the cache controller.
> > >
> > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >
> > Thanks for your patch!
> >
> > > --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > @@ -28,6 +28,7 @@ select:
> > >  properties:
> > >    compatible:
> > >      items:
> > > +      - const: renesas,r9a07g043f-cache
> >
> > This name looks a bit too generic to me, as this is not a generic
> > cache on the R9A07G043F SoC, but specific to the CPU cores.
>
> So "reneasas,r9...-cpu-cache"?

Maybe "renesas,r9a07g043f-riscv-cache" ?

Cheers,
Prabhakar

Re: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Geert Uytterhoeven]

On Mon, 12 May 2025 at 12:05, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Mon, May 12, 2025 at 10:59 AM Conor Dooley <conor@kernel.org> wrote:
> > On Mon, May 12, 2025 at 11:01:26AM +0200, Geert Uytterhoeven wrote:
> > > On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@kernel.org> wrote:
> > > > From: Conor Dooley <conor.dooley@microchip.com>
> > > >
> > > > When the binding was originally written, it was assumed that all
> > > > ax45mp-caches had the same properties etc. This has turned out to be
> > > > incorrect, as the QiLai SoC has a different number of cache-sets.
> > > >
> > > > Add a specific compatible for the RZ/Five for property enforcement and
> > > > in case there turns out to be additional differences between these
> > > > implementations of the cache controller.
> > > >
> > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > > @@ -28,6 +28,7 @@ select:
> > > >  properties:
> > > >    compatible:
> > > >      items:
> > > > +      - const: renesas,r9a07g043f-cache
> > >
> > > This name looks a bit too generic to me, as this is not a generic
> > > cache on the R9A07G043F SoC, but specific to the CPU cores.
> >
> > So "reneasas,r9...-cpu-cache"?
>
> Maybe "renesas,r9a07g043f-riscv-cache" ?

"renesas,r9a07g043f-ax45mp-cache"?

There don't seem to be many vendor-specific derivatives of standardized
caches, except for "brcm,bcm11351-a2-pl310-cache".

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Conor Dooley]

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On Mon, May 12, 2025 at 01:05:13PM +0200, Geert Uytterhoeven wrote:
> On Mon, 12 May 2025 at 12:05, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > On Mon, May 12, 2025 at 10:59 AM Conor Dooley <conor@kernel.org> wrote:
> > > On Mon, May 12, 2025 at 11:01:26AM +0200, Geert Uytterhoeven wrote:
> > > > On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@kernel.org> wrote:
> > > > > From: Conor Dooley <conor.dooley@microchip.com>
> > > > >
> > > > > When the binding was originally written, it was assumed that all
> > > > > ax45mp-caches had the same properties etc. This has turned out to be
> > > > > incorrect, as the QiLai SoC has a different number of cache-sets.
> > > > >
> > > > > Add a specific compatible for the RZ/Five for property enforcement and
> > > > > in case there turns out to be additional differences between these
> > > > > implementations of the cache controller.
> > > > >
> > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > > > @@ -28,6 +28,7 @@ select:
> > > > >  properties:
> > > > >    compatible:
> > > > >      items:
> > > > > +      - const: renesas,r9a07g043f-cache
> > > >
> > > > This name looks a bit too generic to me, as this is not a generic
> > > > cache on the R9A07G043F SoC, but specific to the CPU cores.
> > >
> > > So "reneasas,r9...-cpu-cache"?
> >
> > Maybe "renesas,r9a07g043f-riscv-cache" ?
> 
> "renesas,r9a07g043f-ax45mp-cache"?
> 
> There don't seem to be many vendor-specific derivatives of standardized
> caches, except for "brcm,bcm11351-a2-pl310-cache".

The sifive stuff is all "vendor,soc-cache" into "sifive,ccache" but
there's little ambiguity about there being an arm version of the same
soc there. I don't mind the "renesas,r9...-ax45mp-cache" one you
suggested, feels better than "riscv" to me.

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Re: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

[Lad, Prabhakar]

Hi Geert,

On Mon, May 12, 2025 at 12:05 PM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> On Mon, 12 May 2025 at 12:05, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > On Mon, May 12, 2025 at 10:59 AM Conor Dooley <conor@kernel.org> wrote:
> > > On Mon, May 12, 2025 at 11:01:26AM +0200, Geert Uytterhoeven wrote:
> > > > On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@kernel.org> wrote:
> > > > > From: Conor Dooley <conor.dooley@microchip.com>
> > > > >
> > > > > When the binding was originally written, it was assumed that all
> > > > > ax45mp-caches had the same properties etc. This has turned out to be
> > > > > incorrect, as the QiLai SoC has a different number of cache-sets.
> > > > >
> > > > > Add a specific compatible for the RZ/Five for property enforcement and
> > > > > in case there turns out to be additional differences between these
> > > > > implementations of the cache controller.
> > > > >
> > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > > > @@ -28,6 +28,7 @@ select:
> > > > >  properties:
> > > > >    compatible:
> > > > >      items:
> > > > > +      - const: renesas,r9a07g043f-cache
> > > >
> > > > This name looks a bit too generic to me, as this is not a generic
> > > > cache on the R9A07G043F SoC, but specific to the CPU cores.
> > >
> > > So "reneasas,r9...-cpu-cache"?
> >
> > Maybe "renesas,r9a07g043f-riscv-cache" ?
>
> "renesas,r9a07g043f-ax45mp-cache"?
>
Sounds good to me.

Cheers,
Prabhakar