From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C00032C2ABE; Tue, 13 May 2025 17:50:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747158618; cv=none; b=iaUnrNjljHCvVS4V32jW2cRAEPtGPPpC9ixFLBe8tInYJxaCElCCa5+NHq4bGSofrrptmyv/BCrY4rTUOWT6N+LaNgqBU3QDJ1kOGvIFNiPX1bNlyEhUKkG2Zeg/nNPyjE0XkjTr8hNTPpkvfSnY0Bt+gNzyToq56F9VPXnb7ho= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747158618; c=relaxed/simple; bh=U2EbKqHb+bPlK+hv9U4zW5BxtRVz8s8HpEo+8XdTKeU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KdDrfBn4iq48Zs1y+KDBgRrnxnTYPBbKBJyQc01aCdFFrVxZx0ipt9XznFsDFyHtzkiturE4vor5m4TSk1jRHwtusx12B2/HawZE6876DwN96J/XWGv7BWgHJ/24XdBL9woU4+YYdIVfZtwPbbu9wWtjGA2cMg/s3l+OMfc2bww= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pD9ah0D/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pD9ah0D/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CADADC4CEEF; Tue, 13 May 2025 17:50:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747158617; bh=U2EbKqHb+bPlK+hv9U4zW5BxtRVz8s8HpEo+8XdTKeU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pD9ah0D/4DL1PAGbWWv/3JSdIlnowg1pKqw5vdOse5aiySbKiRdncbRc5K8l2BGm1 VWhHkMM7ZoW0DtkQDAEKkH5a9S+OC5zJm7Q5IlQaKVboM0+sFf9lpFZOnVC0Em5Jh9 +GWtcWZvY+erO8otYw2PbahkE9VpjKiqTOKOhjgNUmp+FG9fu/nPv+I3PyicaExMWt eAF8Il9Hrd5iiwwZvZPbveWDPKxZOFELaUkItRguUvJhm0GHw74727i9BV4ThBmwQc s89d/f8oZjE4ysci2+7+yOzilw9/diw1Flja8Do+Eowngg75MUaF35nc+UQ1lmVm/t iBGWAQ6iY9yjg== From: Lorenzo Pieralisi Date: Tue, 13 May 2025 19:48:16 +0200 Subject: [PATCH v4 23/26] irqchip/gic-v5: Enable GICv5 SMP booting Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250513-gicv5-host-v4-23-b36e9b15a6c3@kernel.org> References: <20250513-gicv5-host-v4-0-b36e9b15a6c3@kernel.org> In-Reply-To: <20250513-gicv5-host-v4-0-b36e9b15a6c3@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Set up IPIs by allocating IPI IRQs for all cpus and call into arm64 core code to initialise IPIs IRQ descriptors and request the related IRQ. Implement hotplug callback to enable interrupts on a cpu and register the cpu with an IRS. Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v5.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index 42098cc20df5089ec0a5e0ee86246a3085878a87..599ce7009ca40ba8b87f7e63a56647223ab3f99f 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -5,6 +5,7 @@ #define pr_fmt(fmt) "GICv5: " fmt +#include #include #include #include @@ -908,6 +909,8 @@ static void gicv5_cpu_enable_interrupts(void) write_sysreg_s(cr0, SYS_ICC_CR0_EL1); } +static int base_ipi_virq; + static int gicv5_starting_cpu(unsigned int cpu) { if (WARN(!gicv5_cpuif_has_gcie(), @@ -919,6 +922,22 @@ static int gicv5_starting_cpu(unsigned int cpu) return gicv5_irs_register_cpu(cpu); } +static void __init gicv5_smp_init(void) +{ + unsigned int num_ipis = GICV5_IPIS_PER_CPU * nr_cpu_ids; + + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, + "irqchip/arm/gicv5:starting", + gicv5_starting_cpu, NULL); + + base_ipi_virq = irq_domain_alloc_irqs(gicv5_global_data.ipi_domain, + num_ipis, NUMA_NO_NODE, NULL); + if (WARN(base_ipi_virq <= 0, "IPI IRQ allocation was not successful")) + return; + + set_smp_ipi_range_percpu(base_ipi_virq, GICV5_IPIS_PER_CPU, nr_cpu_ids); +} + static void __init gicv5_free_domains(void) { if (gicv5_global_data.ppi_domain) @@ -1040,6 +1059,8 @@ static int __init gicv5_of_init(struct device_node *node, struct device_node *pa if (ret) goto out_int; + gicv5_smp_init(); + return 0; out_int: gicv5_cpu_disable_interrupts(); -- 2.48.0