From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1821242D6E for ; Tue, 13 May 2025 09:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129832; cv=none; b=MqHBnvmCtekXq+cv8s7KShPVT1Q2ix8MrJyJYCfRlpeDoDRMjfzSZFrXbtxdARvTWNmrzVnBblBFwjzaISTap3+l+wqrL/71ycceZwtWOXLpBhmZ74huN1426WKAg16YVvhtWIRhuiD+Wel5/6YUWKjQGejFXHPjxBiIvOD5YJc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129832; c=relaxed/simple; bh=MUNzFZca4jP1Wzj7p7OSBhZbTeKUQVOelMr5pj0uSLM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tcXX99Qi+N0RWLGec9UJ8MhrHLN/6ddkHFevfv26XjM3V1z/NsRV8PJrTjQhDwjXsGiOUvjVfqNa+/JTvntOJ1U9brwEJPdj1BA1wvL1jvgTMzv6BGv4WgTSl7W0FyXdh/ubDzTKUYquMCrLp/Wlke92ADI9dQHgoehPnxUnz+U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9ntro044935 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:55 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:55 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v3 9/9] riscv: defconfig: enable Andes SoC Date: Tue, 13 May 2025 17:49:33 +0800 Message-ID: <20250513094933.1631493-10-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 54D9ntro044935 Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index eea825ee58e1..29a97cbf4ee6 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=y +CONFIG_ARCH_ANDES=y CONFIG_ARCH_MICROCHIP=y CONFIG_ARCH_SIFIVE=y CONFIG_ARCH_SOPHGO=y -- 2.34.1