From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E09FC23C502 for ; Tue, 13 May 2025 09:50:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129842; cv=none; b=Ha+qNLRMwj9zljqrg5JnffZJh6Z4wIoEe1VewjyhYGegVu0Vk57thcCUAxVh31Rnawx7A631v4KTdaPT380du3n+hKcR0HddIwnmS979J8huBU4rHWjtjhVN2mQC5XYxREH0veNakcuB71GZXB0n/ODqM9oLwipmXh0VXn2LXmo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129842; c=relaxed/simple; bh=TUKwT3goQGW7BgcxvA/BGgnrg1MvnylmSbViGWkZyUE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gajFjwTL/R7tZvwxsN/KMZwNVKv81zVZJZ4Pd1G3NO0Gm1YxijDriRdgx2yyU8eF0fUvJLoe+eRK2ErxX8cg9ThFpHGHy7MGCNJpIVGJznaj84Du64iiEHMXGne8ksBXH7u1qao/nP7YguSsk+rifFl483OtZMZbCGAuYvbxoBU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9nqRh044911 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:52 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:51 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v3 6/9] dt-bindings: cache: add QiLai compatible to ax45mp Date: Tue, 13 May 2025 17:49:30 +0800 Message-ID: <20250513094933.1631493-7-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 54D9nqRh044911 Add a new compatible string for ax45mp-cache on QiLai SoC. Also, add allOf constraints to enforce specific cache-sets and cache-size values for each compatible string. Signed-off-by: Ben Zong-You Xie --- .../cache/andestech,ax45mp-cache.yaml | 52 +++++++++++++++++-- 1 file changed, 47 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index df8bba14f758..dc03ffae6c9f 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -28,7 +28,9 @@ select: properties: compatible: items: - - const: renesas,r9a07g043f-ax45mp-cache + - enum: + - andestech,qilai-ax45mp-cache + - renesas,r9a07g043f-ax45mp-cache - const: andestech,ax45mp-cache - const: cache @@ -44,11 +46,9 @@ properties: cache-level: const: 2 - cache-sets: - enum: [1024, 2048] + cache-sets: true - cache-size: - enum: [131072, 262144, 524288, 1048576, 2097152] + cache-size: true cache-unified: true @@ -66,7 +66,49 @@ required: - cache-size - cache-unified +allOf: + - if: + properties: + compatible: + contains: + const: andestech,qilai-ax45mp-cache + + then: + properties: + cache-sets: + const: 2048 + cache-size: + const: 2097152 + + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043f-ax45mp-cache + + then: + properties: + cache-sets: + const: 1024 + cache-size: + const: 262144 + examples: + - | + #include + + l2_cache: cache-controller@200000 { + compatible = "andestech,qilai-ax45mp-cache", "andestech,ax45mp-cache", + "cache"; + reg = <0x00200000 0x100000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + }; + - | #include -- 2.34.1