From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBF05186E20; Wed, 14 May 2025 14:48:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747234096; cv=none; b=bP1ckvbcTSX3kByvrgFXDqF/7OXQ7jEfBc+1LB77GympyCT1CsovLttzBwZT+a6sP2C5Gh5vy3fvq11moBhSrWzkTF+CbPOyccKtHrJHmSa7FWpZ7oCH5BzxlzDUBUDWgmVIIANSZ2H2iSaR/LdIC2plGcC+Uvke7au8j5ggm7k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747234096; c=relaxed/simple; bh=hOT0ZYvtO3HqOYhLkP76vJyO3R2nnEC5weeQ8KdNS1Q=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=i8wtKqOfVF2rmnz5yat7Aq0qCypw1p58qWRByLry+xJ04vWusQoSMXMEwRijU9Mch683W8iKkViGg79OquJfeFVY0bAIuXTpkQgUZFN561UD5laF7ve5wIl1t+uR1xS7A1+yseZ/6BbqS+v9ui8TTlgJYZu29RKX8v+XK7oLqZg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=1rt9Z9KX; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="1rt9Z9KX" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54EDDNKV014107; Wed, 14 May 2025 16:47:47 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=selector1; bh=jlu2VRrBqc+sWbmBDvpfmK i7EGi8p2tPIIEHbOtQl/0=; b=1rt9Z9KXMPEx+/IL02gfKnAtKkb8VRhDWlCaTR 7//AQSzkyFFx2r1VIn4xHL22sdPtssPBzhXEvl1tHLpPFBZL826qnyW3UfFPMecz DO+zLRaHtGKZK3E/a7FaccQpXDMXGbHAi0COVNMKP/0I4b8NV6xWxnYXAj1/QvAe IYn+u8T4pStZLBCXvgn50q87Q6lmaH17DXcq8kUF52WeYkgcUGqqg38h8AnUSFSY BKJWaNl2EuPXa5paWVckLVuZMW6rb+xJzXDwPUkc+3a01pEczg2zVHBFhBI1YRi0 2G0vGaN4L8KKk/vNt7TZo6HmML7rUW2AaXw6PY+GMbdXDAQQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 46mbds4b40-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 May 2025 16:47:47 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5125F40055; Wed, 14 May 2025 16:46:20 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7A36CAF0535; Wed, 14 May 2025 16:44:32 +0200 (CEST) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 14 May 2025 16:44:32 +0200 From: Christian Bruel To: , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v10 0/9] Add STM32MP25 PCIe drivers Date: Wed, 14 May 2025 16:44:19 +0200 Message-ID: <20250514144428.3340709-1-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 Changes in v10; - Update pcie_ep bindings with dbi2 and atu regs, thus remove Reviewed-by and Acked-by. Changes in v9: - Describe atu and dbi2 shadowed registers in pcie_ep node Address RC and EP drivers comments from Manivanna: - Use dev_error_probe() for pm_runtime_enable() calls - Reword Kconfig help message - Move pm_runtime_get_noresume() before devm_pm_runtime_enable() Changes in v8: - Whitespace in comment Changes in v7: - Use device_init_wakeup to enable wakeup - Fix comments (Bjorn) Changes in v6: - Call device_wakeup_enable() to fix WAKE# wakeup. Address comments from Manivanna: - Fix/Add Comments - Fix DT indents - Remove dw_pcie_ep_linkup() in EP start link - Add PCIE_T_PVPERL_MS delay in RC PERST# deassert Changes in v5: Address driver comments from Manivanna: - Use dw_pcie_{suspend/resume}_noirq instead of private ones. - Move dw_pcie_host_init() to probe - Add stm32_remove_pcie_port cleanup function - Use of_node_put in stm32_pcie_parse_port - Remove wakeup-source property - Use generic dev_pm_set_dedicated_wake_irq to support wake# irq Changes in v4: Address bindings comments Rob Herring - Remove phy property form common yaml - Remove phy-name property - Move wake_gpio and reset_gpio to the host root port Changes in v3: Address comments from Manivanna, Rob and Bjorn: - Move host wakeup helper to dwc core (Mani) - Drop num-lanes=<1> from bindings (Rob) - Fix PCI address of I/O region (Mani) - Moved PHY to a RC rootport subsection (Bjorn, Mani) - Replaced dma-limit quirk by dma-ranges property (Bjorn) - Moved out perst assert/deassert from start/stop link (Mani) - Drop link_up test optim (Mani) - DT and comments rephrasing (Bjorn) - Add dts entries now that the combophy entries has landed - Drop delaying Configuration Requests Changes in v2: - Fix st,stm32-pcie-common.yaml dt_binding_check Changes in v1: Address comments from Rob Herring and Bjorn Helgaas: - Drop st,limit-mrrs and st,max-payload-size from this patchset - Remove single reset and clocks binding names and misc yaml cleanups - Split RC/EP common bindings to a separate schema file - Use correct PCIE_T_PERST_CLK_US and PCIE_T_RRS_READY_MS defines - Use .remove instead of .remove_new - Fix bar reset sequence in EP driver - Use cleanup blocks for error handling - Cosmetic fixes Christian Bruel (9): dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings PCI: stm32: Add PCIe host support for STM32MP25 dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings PCI: stm32: Add PCIe Endpoint support for STM32MP25 MAINTAINERS: add entry for ST STM32MP25 PCIe drivers arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi arm64: dts: st: Add PCIe Root Complex mode on stm32mp251 arm64: dts: st: Add PCIe Endpoint mode on stm32mp251 arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board .../bindings/pci/st,stm32-pcie-common.yaml | 33 ++ .../bindings/pci/st,stm32-pcie-ep.yaml | 73 ++++ .../bindings/pci/st,stm32-pcie-host.yaml | 112 +++++ MAINTAINERS | 7 + arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 20 + arch/arm64/boot/dts/st/stm32mp251.dtsi | 59 +++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 21 + drivers/pci/controller/dwc/Kconfig | 24 + drivers/pci/controller/dwc/Makefile | 2 + drivers/pci/controller/dwc/pcie-stm32-ep.c | 411 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.c | 364 ++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.h | 16 + 12 files changed, 1142 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml create mode 100644 drivers/pci/controller/dwc/pcie-stm32-ep.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.h base-commit: aa94665adc28f3fdc3de2979ac1e98bae961d6ca -- 2.34.1