Re: [PATCH v3 3/4] dt-bindings: iio: adc: add ad7405

[Jonathan Cameron <jic23@kernel.org>]

On Fri, 16 May 2025 13:58:03 +0300
Pop Ioan Daniel <pop.ioan-daniel@analog.com> wrote:

> Add devicetree bindings for ad7405/adum770x family.
> 
> Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
> ---
> changes in v2:
>  - fix properties: clocks issue
>  .../bindings/iio/adc/adi,ad7405.yaml          | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7405.yaml
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7405.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7405.yaml
> new file mode 100644
> index 000000000000..939de3bd6f26
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7405.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2025 Analog Devices Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/adi,ad7405.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AD7405 family
> +
> +maintainers:
> +  - Dragos Bogdan <dragos.bogdan@analog.com>
> +  - Pop Ioan Daniel <pop.ioan-daniel@analog.com>
> +
> +description: |
> +  Analog Devices AD7405 is a high performance isolated ADC, 1-channel,
> +  16-bit with a second-order Σ-Δ modulator that converts an analog input signal
> +  into a high speed, single-bit data stream.
> +
> +  https://www.analog.com/media/en/technical-documentation/data-sheets/ad7405.pdf
> +  https://www.analog.com/media/en/technical-documentation/data-sheets/adum7701.pdf
> +  https://www.analog.com/media/en/technical-documentation/data-sheets/adum7702.pdf
> +  https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM7703.pdf
> +
> +properties:
> +  compatible:
> +    enum:
> +      - adi,ad7405
> +      - adi,adum7701
> +      - adi,adum7702
> +      - adi,adum7703
> +
> +  clocks:
> +    maxItems: 1

The closest part we have to this (LVDS bus etc) that I could find was
the ad7625.  That does use an explicit clock but there is more going
on as it also has a pwm connected to gate that clock so maybe isn't
an idea example to follow.

As you will see in the driver review I just sent I'm wondering if an
explicit clock is a separate thing or considered part of the lvds bus.

It's definitely wired to the ADC as a clock but it's also (I think) either
wired up to the IP we map to the backend (from software point of view)
or generated by that.

I don't think this device is using an LVDS encoding to allow the clock
to be established from the data lines alone? 8b/10b or similar (if it were then the
clock to the ADC only description would be correct choice).

Perhaps this device is one that needs docs in the kernel to talk us
through how the signalling is working.

Jonathan

> +
> +  vdd1-supply: true
> +
> +  vdd2-supply: true
> +
> +  io-backends:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - clocks
> +  - vdd1-supply
> +  - vdd2-supply
> +  - io-backends
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    adc {
> +        compatible = "adi,ad7405";
> +        clocks = <&axi_clk_gen 0>;
> +        vdd1-supply = <&vdd1>;
> +        vdd2-supply = <&vdd2>;
> +        io-backends = <&iio_backend>;
> +    };
> +...