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From: Conor Dooley <conor@kernel.org>
To: adrianhoyin.ng@altera.com
Cc: dinguyen@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, Eugeniy.Paltsev@synopsys.com,
	vkoul@kernel.org, dmaengine@vger.kernel.org,
	devicetree@vger.kernel.org,
	Matthew Gerlach <matthew.gerlach@altrera.com>
Subject: Re: [PATCH v2 1/4] dt-bindings: dma: snps,dw-axi-dmac: Add iommus dma-coherent and dma bit-mask quirk
Date: Mon, 19 May 2025 17:09:50 +0100	[thread overview]
Message-ID: <20250519-palm-clunky-d10f84e7f37d@spud> (raw)
In-Reply-To: <c9d1ae618b43b328b3b8775334987e5acdaf2490.1747630638.git.adrianhoyin.ng@altera.com>

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On Mon, May 19, 2025 at 01:09:38PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Intel Agilex5 address bus only supports up to 40 bits. Add dma-bit-mask
> property to allow configuration of dma bit-mask size. Add iommu property
> for SMMU support. Add dma-coherent property for cache coherent support.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
> ---
>  .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml   | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 935735a59afd..f0a54a1031e7 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -42,6 +42,9 @@ properties:
>      minItems: 1
>      maxItems: 8
>  
> +  iommus:
> +    maxItems: 1
> +
>    clocks:
>      items:
>        - description: Bus Clock
> @@ -61,6 +64,8 @@ properties:
>  
>    dma-noncoherent: true
>  
> +  dma-coherent: true
> +
>    resets:
>      minItems: 1
>      maxItems: 2
> @@ -101,6 +106,14 @@ properties:
>      minimum: 1
>      maximum: 256
>  
> +  snps,dma-bit-mask:

This property seems incorrectly named to me, from the description this
does not seem like a bitmask cos you cannot have a 64-bit bitmask in a
u32... Instead, this property is being fed into the DMA_BIT_MASK()
macro, and is actually just the number of bits to use for dma (as the
description correctly points out). Please adjust the naming accordingly.

> +    description:
> +      Defines the number of addressable bits for DMA.
> +      If this property is missing, the default 64bit will be used.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 32
> +    maximum: 64

Missing a default: 64, that's what you should do rather than mention in
text form.

> +
>  required:
>    - compatible
>    - reg
> -- 
> 2.49.GIT
> 

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  reply	other threads:[~2025-05-19 16:09 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-19  5:09 [PATCH v2 0/4] agilex5: Update agilex5 device tree and device tree bindings adrianhoyin.ng
2025-05-19  5:09 ` [PATCH v2 1/4] dt-bindings: dma: snps,dw-axi-dmac: Add iommus dma-coherent and dma bit-mask quirk adrianhoyin.ng
2025-05-19 16:09   ` Conor Dooley [this message]
2025-05-19  5:09 ` [PATCH v2 2/4] dt-bindings: mtd: cadence: Add iommus and dma-coherent properties adrianhoyin.ng
2025-05-19  5:09 ` [PATCH v2 3/4] arm64: dts: socfpga: agilex5: Update Agilex5 DTSI and DTS adrianhoyin.ng
2025-05-19  5:09 ` [PATCH v2 4/4] dma: dw-axi-dmac: Add support for dma-bit-mask property adrianhoyin.ng

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