Re: [PATCH v2] dt-bindings: display: bridge: renesas,dsi: allow properties from dsi-controller

[Conor Dooley <conor@kernel.org>]

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On Tue, May 20, 2025 at 11:11:12AM -0400, Hugo Villeneuve wrote:
> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> 
> Allow to inherit valid properties from the dsi-controller. This fixes the
> following warning when adding a panel property:
> 
> rzg2lc.dtb: dsi@10850000: '#address-cells', '#size-cells', 'panel@0' do not
>     match any of the regexes: 'pinctrl-[0-9]+'
>     from schema $id:
>         http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
> 
> Also add a panel property to the example.

I don't think adding the example should be in the same patch as a fix.

> 
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> ---
> V1 -> V2: add separate example
> ---
>  .../bindings/display/bridge/renesas,dsi.yaml  | 67 ++++++++++++++++++-
>  1 file changed, 66 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> index e08c24633926b..5a99d9b9635e7 100644
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> @@ -128,7 +128,7 @@ required:
>    - power-domains
>    - ports
>  
> -additionalProperties: false
> +unevaluatedProperties: false
>  
>  examples:
>    - |
> @@ -180,4 +180,69 @@ examples:
>              };
>          };
>      };
> +
> +  - |
> +    #include <dt-bindings/gpio/gpio.h>
> +
> +    dsi1: dsi@10860000 {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
> +        reg = <0x10860000 0x20000>;
> +        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "seq0", "seq1", "vin1", "rcv",
> +                          "ferr", "ppi", "debug";
> +        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
> +                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
> +        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
> +        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
> +                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
> +                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
> +        reset-names = "rst", "arst", "prst";
> +        power-domains = <&cpg>;
> +
> +        panel@0 {
> +            compatible = "rocktech,jh057n00900";
> +            reg = <0>;
> +            vcc-supply = <&reg_2v8_p>;
> +            iovcc-supply = <&reg_1v8_p>;
> +            reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
> +
> +            port {
> +                panel_in: endpoint {
> +                    remote-endpoint = <&dsi1_out>;
> +                };
> +            };
> +        };
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@0 {
> +                reg = <0>;
> +                dsi1_in: endpoint {
> +                    remote-endpoint = <&du_out_dsi1>;
> +                };
> +            };
> +
> +            port@1 {
> +                reg = <1>;
> +                dsi1_out: endpoint {
> +                    data-lanes = <1 2 3 4>;
> +                    remote-endpoint = <&panel_in>;
> +                };
> +            };
> +        };
> +    };
>  ...
> 
> base-commit: 7c1a9408ce5f34ded5a85db81cf80e0975901685
> -- 
> 2.39.5
> 

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