* [PATCH 0/1] arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5
@ 2025-05-20 0:33 John Clark
2025-05-20 0:33 ` [PATCH 1/1] " John Clark
0 siblings, 1 reply; 3+ messages in thread
From: John Clark @ 2025-05-20 0:33 UTC (permalink / raw)
To: heiko, robh, krzk+dt, conor+dt
Cc: nicolas.frattaroli, detlev.casanova, linux-rockchip,
linux-arm-kernel, devicetree, John Clark
This patch updates the RK3576 ArmSoM Sige5 device tree to use standard
Ethernet PHY reset properties. It replaces the deprecated Synopsys-specific
snps,reset-gpio, snps,reset-active-low, and snps,reset-delays-us properties
in the gmac0 and gmac1 nodes with the standard reset-gpios, reset-assert-us,
and reset-deassert-us properties in the rgmii_phy0 and rgmii_phy1 nodes.
It also adds pinctrl properties to the PHY nodes and defines gmac0_rst and
gmac1_rst in the pinctrl node. The phy-handle property is reordered for
consistency.
The changes have been tested on the ArmSoM Sige5 board, confirming proper
Ethernet functionality.
Signed-off-by: John Clark <inindev@gmail.com>
---
John Clark (1):
arm64: dts: rockchip: Use standard PHY reset properties for RK3576
ArmSoM Sige5
.../boot/dts/rockchip/rk3576-armsom-sige5.dts | 35 +++++++++++--------
1 file changed, 21 insertions(+), 14 deletions(-)
--
2.39.5
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/1] arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5
2025-05-20 0:33 [PATCH 0/1] arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5 John Clark
@ 2025-05-20 0:33 ` John Clark
2025-06-09 10:23 ` Heiko Stuebner
0 siblings, 1 reply; 3+ messages in thread
From: John Clark @ 2025-05-20 0:33 UTC (permalink / raw)
To: heiko, robh, krzk+dt, conor+dt
Cc: nicolas.frattaroli, detlev.casanova, linux-rockchip,
linux-arm-kernel, devicetree, John Clark
Replace deprecated snps,reset-gpio, snps,reset-active-low, and
snps,reset-delays-us in gmac0 and gmac1 nodes with standard reset-gpios,
reset-assert-us, and reset-deassert-us in rgmii_phy0 and rgmii_phy1 nodes.
Add pinctrl properties to PHY nodes and define gmac0_rst and gmac1_rst in
pinctrl node. Reorder phy-handle for consistency.
Signed-off-by: John Clark <inindev@gmail.com>
---
.../boot/dts/rockchip/rk3576-armsom-sige5.dts | 35 +++++++++++--------
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
index b09e789c75c4..34e51cd71eac 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
@@ -218,30 +218,20 @@ &cpu_l0 {
&gmac0 {
phy-mode = "rgmii-id";
clock_in_out = "output";
-
- snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 20000 100000>;
-
+ phy-handle = <&rgmii_phy0>;
pinctrl-names = "default";
pinctrl-0 = <ð0m0_miim
ð0m0_tx_bus2
ð0m0_rx_bus2
ð0m0_rgmii_clk
ð0m0_rgmii_bus>;
-
- phy-handle = <&rgmii_phy0>;
status = "okay";
};
&gmac1 {
phy-mode = "rgmii-id";
clock_in_out = "output";
-
- snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 20000 100000>;
-
+ phy-handle = <&rgmii_phy1>;
pinctrl-names = "default";
pinctrl-0 = <ð1m0_miim
ð1m0_tx_bus2
@@ -249,8 +239,6 @@ ð1m0_rx_bus2
ð1m0_rgmii_clk
ð1m0_rgmii_bus
ðm0_clk1_25m_out>;
-
- phy-handle = <&rgmii_phy1>;
status = "okay";
};
@@ -680,6 +668,11 @@ rgmii_phy0: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
clocks = <&cru REFCLKO25M_GMAC0_OUT>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
};
};
@@ -688,6 +681,11 @@ rgmii_phy1: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
clocks = <&cru REFCLKO25M_GMAC1_OUT>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
};
};
@@ -700,6 +698,15 @@ &pcie0 {
};
&pinctrl {
+ gmac {
+ gmac0_rst: gmac0-rst {
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ gmac1_rst: gmac1-rst {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
headphone {
hp_det: hp-det {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
--
2.39.5
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5
2025-05-20 0:33 ` [PATCH 1/1] " John Clark
@ 2025-06-09 10:23 ` Heiko Stuebner
0 siblings, 0 replies; 3+ messages in thread
From: Heiko Stuebner @ 2025-06-09 10:23 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, John Clark
Cc: Heiko Stuebner, nicolas.frattaroli, detlev.casanova,
linux-rockchip, linux-arm-kernel, devicetree
On Mon, 19 May 2025 20:33:32 -0400, John Clark wrote:
> Replace deprecated snps,reset-gpio, snps,reset-active-low, and
> snps,reset-delays-us in gmac0 and gmac1 nodes with standard reset-gpios,
> reset-assert-us, and reset-deassert-us in rgmii_phy0 and rgmii_phy1 nodes.
> Add pinctrl properties to PHY nodes and define gmac0_rst and gmac1_rst in
> pinctrl node. Reorder phy-handle for consistency.
>
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5
commit: 63136c6fecf44b4f2cb458b01cfdbc2cb0ddd29c
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-05-20 0:33 ` [PATCH 1/1] " John Clark
2025-06-09 10:23 ` Heiko Stuebner
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