From: Shubhi Garg <shgarg@nvidia.com>
To: <jonathanh@nvidia.com>, <lee@kernel.org>, <robh@kernel.org>,
<krzk@kernel.org>, <alexandre.belloni@bootlin.com>,
<thierry.reding@gmail.com>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Shubhi Garg <shgarg@nvidia.com>
Subject: [PATCH V2 6/6] MAINTAINERS: Add NVIDIA VRS PSEQ driver entry
Date: Tue, 20 May 2025 09:08:32 +0000 [thread overview]
Message-ID: <20250520090832.3564104-7-shgarg@nvidia.com> (raw)
In-Reply-To: <20250520090832.3564104-1-shgarg@nvidia.com>
Add NVIDIA VRS (Voltage Regulator Specification) power sequencer driver
entry in MAINTAINERS.
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
---
v2:
- this is a new patch in V2
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 20e07e61a148..aff6a915d5a2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17707,6 +17707,15 @@ S: Maintained
F: drivers/video/fbdev/nvidia/
F: drivers/video/fbdev/riva/
+NVIDIA VRS POWER SEQUENCER
+M: Shubhi Garg <shgarg@nvidia.com>
+L: linux-tegra@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
+F: drivers/mfd/nvidia-vrs-pseq.c
+F: drivers/rtc/rtc-nvidia-vrs-pseq.c
+F: include/linux/mfd/nvidia-vrs-pseq.h
+
NVIDIA WMI EC BACKLIGHT DRIVER
M: Daniel Dadap <ddadap@nvidia.com>
L: platform-driver-x86@vger.kernel.org
--
2.43.0
prev parent reply other threads:[~2025-05-20 9:09 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 9:08 [PATCH V2 0/6] Add NVIDIA VRS PSEQ support Shubhi Garg
2025-05-20 9:08 ` [PATCH V2 1/6] dt-bindings: mfd: add bindings for NVIDIA VRS PSEQ Shubhi Garg
2025-05-21 9:09 ` Krzysztof Kozlowski
2025-05-20 9:08 ` [PATCH V2 2/6] arm64: tegra: Add device-tree node for NVVRS PSEQ Shubhi Garg
2025-05-20 9:08 ` [PATCH V2 3/6] mfd: nvvrs: add NVVRS PSEQ MFD driver Shubhi Garg
2025-05-21 9:12 ` Krzysztof Kozlowski
2025-05-20 9:08 ` [PATCH V2 4/6] rtc: nvvrs: add NVIDIA VRS PSEQ RTC device driver Shubhi Garg
2025-05-21 9:14 ` Krzysztof Kozlowski
2025-06-02 14:47 ` Jon Hunter
2025-05-20 9:08 ` [PATCH V2 5/6] arm64: defconfig: enable NVIDIA VRS PSEQ Shubhi Garg
2025-05-20 9:12 ` Krzysztof Kozlowski
2025-05-20 9:08 ` Shubhi Garg [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250520090832.3564104-7-shgarg@nvidia.com \
--to=shgarg@nvidia.com \
--cc=alexandre.belloni@bootlin.com \
--cc=devicetree@vger.kernel.org \
--cc=jonathanh@nvidia.com \
--cc=krzk@kernel.org \
--cc=lee@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=robh@kernel.org \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).