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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-44fccee6c54sm33682535e9.1.2025.05.27.17.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 17:49:54 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH 3/5] dt-bindings: reset: add binding for Airoha AN7583 SoC reset Date: Wed, 28 May 2025 02:49:16 +0200 Message-ID: <20250528004924.19970-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250528004924.19970-1-ansuelsmth@gmail.com> References: <20250528004924.19970-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add binding for Airoha AN7583 SoC Resets. These are very similar to EN7581 but lack some specific reset line hence the order is different and a dedicated binding is needed. Signed-off-by: Christian Marangi --- .../dt-bindings/reset/airoha,an7583-reset.h | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h diff --git a/include/dt-bindings/reset/airoha,an7583-reset.h b/include/dt-bindings/reset/airoha,an7583-reset.h new file mode 100644 index 000000000000..96cfe11d2943 --- /dev/null +++ b/include/dt-bindings/reset/airoha,an7583-reset.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ + +/* RST_CTRL2 */ +#define AN7583_XPON_PHY_RST 0 +#define AN7583_GPON_OLT_RST 1 +#define AN7583_CPU_TIMER2_RST 2 +#define AN7583_HSUART_RST 3 +#define AN7583_UART4_RST 4 +#define AN7583_UART5_RST 5 +#define AN7583_I2C2_RST 6 +#define AN7583_XSI_MAC_RST 7 +#define AN7583_XSI_PHY_RST 8 +#define AN7583_NPU_RST 9 +#define AN7583_TRNG_MSTART_RST 10 +#define AN7583_DUAL_HSI0_RST 11 +#define AN7583_DUAL_HSI1_RST 12 +#define AN7583_DUAL_HSI0_MAC_RST 13 +#define AN7583_DUAL_HSI1_MAC_RST 14 +#define AN7583_WDMA_RST 15 +#define AN7583_WOE0_RST 16 +#define AN7583_HSDMA_RST 17 +#define AN7583_TDMA_RST 18 +#define AN7583_EMMC_RST 19 +#define AN7583_SOE_RST 20 +#define AN7583_XFP_MAC_RST 21 +#define AN7583_MDIO0 22 +#define AN7583_MDIO1 23 +/* RST_CTRL1 */ +#define AN7583_PCM1_ZSI_ISI_RST 24 +#define AN7583_FE_PDMA_RST 25 +#define AN7583_FE_QDMA_RST 26 +#define AN7583_PCM_SPIWP_RST 27 +#define AN7583_CRYPTO_RST 28 +#define AN7583_TIMER_RST 29 +#define AN7583_PCM1_RST 30 +#define AN7583_UART_RST 31 +#define AN7583_GPIO_RST 32 +#define AN7583_GDMA_RST 33 +#define AN7583_I2C_MASTER_RST 34 +#define AN7583_PCM2_ZSI_ISI_RST 35 +#define AN7583_SFC_RST 36 +#define AN7583_UART2_RST 37 +#define AN7583_GDMP_RST 38 +#define AN7583_FE_RST 39 +#define AN7583_USB_HOST_P0_RST 40 +#define AN7583_GSW_RST 41 +#define AN7583_SFC2_PCM_RST 42 +#define AN7583_PCIE0_RST 43 +#define AN7583_PCIE1_RST 44 +#define AN7583_CPU_TIMER_RST 45 +#define AN7583_PCIE_HB_RST 46 +#define AN7583_XPON_MAC_RST 47 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */ -- 2.48.1