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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3124e399b0fsm1615381a91.30.2025.05.30.10.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 10:47:41 -0700 (PDT) From: Jessica Zhang Subject: [PATCH v2 0/5] dt-bindings: msm/dp: add support for pixel clock to driver another stream Date: Fri, 30 May 2025 10:47:23 -0700 Message-Id: <20250530-dp_mst_bindings-v2-0-f925464d32a8@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIACvvOWgC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyjHQUlJIzE vPSU3UzU4B8JSMDIxNDIKGbUhCfW1wSn5SZl5KZl16sa25qbJaWlmyZmGqUpgTUVVCUmpZZATY xOra2FgDlnKS/YQAAAA== X-Change-ID: 20241202-dp_mst_bindings-7536ffc9ae2f To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Mahadevan , Krishna Manikandan , Konrad Dybcio , Danila Tikhonov Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Yongxing Mou , Jessica Zhang X-Mailer: b4 0.15-dev-64971 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748627260; l=2624; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=6uc2UGeYDKojb28VLnUtXsaqjBTpOdr4JI5m+IvoZFs=; b=B4JARvTLryhXsb9dR+6G59wuZvScg2Y7mSDEApXdzmOtc2rUFkH0me1aDfAEfkCSfEPjF2sfe TCooErK5xB4Bc/Yi3hAq/l+BrCIKAkTYbHRNCwluTVfQot2e0Z9hwj7 X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDE1NiBTYWx0ZWRfX1kH9vhyQ1o03 T6qCbs+NDmyTu8HtQztlbGxJ9f5033cvK9DlmoQf1wxCH71BE7ivv5FrQhZN+5e9GdaQEgXkcij qxx2kvcjlu102GFnl5CGR87UzsnEc42QhNMkpD0KLV/lea9AP7qzmZrSApVlvdaOwaCZqmqiU1w ldNCndPgGx3iyuZRcTQ7R9gENClp+8HmjNpN/4Rpzn11JqRuj+iBsSDIL9J/NcnorFwskqz9oQ8 bKROjdhIJicQjLzNtw3sZC3Xc9hHoQ/ti0uwZwHZ98tszBOGbw0Z9CMBvfcBUNrLUDH9MBzs8kQ Cofj9prE9S0HyO1cOACJGmfqTMQjBnf6W9LaUPoXeLTOxbHKFaDfx+D28u+HmUL+WWmmtQQ7ZBb 9W/HKHYPwolVgNm98r8XVgt69tTII8lUkUY87gBiP8LiuCvi0IkA+IxZ47fM2EadsQCl6lH4 X-Authority-Analysis: v=2.4 cv=Fes3xI+6 c=1 sm=1 tr=0 ts=6839ef3f cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=BHNpFwMvo4D9IzoZi8gA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: x5WzBWwoRegN1ZEtUG6VBhI4m-tczmhw X-Proofpoint-ORIG-GUID: x5WzBWwoRegN1ZEtUG6VBhI4m-tczmhw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_08,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 impostorscore=0 phishscore=0 clxscore=1011 lowpriorityscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=867 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300156 On some MSM chipsets, the display port controller is capable of supporting two streams. To drive the second stream, the pixel clock for the corresponding stream needs to be enabled. In order to add the bindings for the pixel clock for the second stream, fixup the documentation of some of the bindings to clarify exactly which stream they correspond to, then add the new bindings and make corresponding changes to the relevant device trees. --- Changes in v2: - Rebased on top of next-20250523 - Dropped merged maintainer patch - Remove assigned-clock-parents from sm7150-mdss.yaml - Added a patch to make the corresponding dts change to add pixel 1 stream - Squashed pixel 0 and pixel 1 stream binding patches (Krzysztof) - Drop assigned-clock-parents bindings for dp-controller (Krzysztof) - Updated dp-controller.yaml to include all chipsets that support stream 1 pixel clock (Krzysztof) - Added missing minItems and if statement (Krzysztof) --- Abhinav Kumar (4): dt-bindings: Fixup x1e80100 to add DP MST support dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding dt-bindings: display/msm: drop assigned-clock-parents for dp controller dt-bindings: display/msm: add stream 1 pixel clock binding Jessica Zhang (1): arm64: dts: qcom: Add pixel 1 stream for displayport .../bindings/display/msm/dp-controller.yaml | 45 +++++++++++--- .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 +-- .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 11 ++-- .../bindings/display/msm/qcom,sc7180-mdss.yaml | 1 - .../bindings/display/msm/qcom,sc7280-mdss.yaml | 11 ++-- .../bindings/display/msm/qcom,sm7150-mdss.yaml | 2 - .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 18 +++--- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 26 +++++--- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 ++++-- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++------- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++- arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++- arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 ++- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 31 +++++++--- include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 + 16 files changed, 197 insertions(+), 92 deletions(-) --- base-commit: daf70030586cf0279a57b58a94c32cfe901df23d change-id: 20241202-dp_mst_bindings-7536ffc9ae2f Best regards, -- Jessica Zhang