From: Sumit Gupta <sumitg@nvidia.com>
To: <treding@nvidia.com>, <jonathanh@nvidia.com>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <--to=tbergstrom@nvidia.com>, <bbasu@nvidia.com>, <sumitg@nvidia.com>
Subject: [Patch 3/8] soc: tegra: cbb: make error interrupt enable and status per SoC
Date: Fri, 30 May 2025 19:03:31 +0530 [thread overview]
Message-ID: <20250530133336.1419971-4-sumitg@nvidia.com> (raw)
In-Reply-To: <20250530133336.1419971-1-sumitg@nvidia.com>
Make the error interrupt enable and error status fields as per SoC.
Both these fields can change for different SoC's. Moving them to per
SoC data helps to set or clear the required bits only for a SoC.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/soc/tegra/cbb/tegra234-cbb.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c
index 5d04ed3b2d50..6116221f0ca6 100644
--- a/drivers/soc/tegra/cbb/tegra234-cbb.c
+++ b/drivers/soc/tegra/cbb/tegra234-cbb.c
@@ -102,6 +102,8 @@ struct tegra234_cbb_fabric {
const int max_errors;
const struct tegra234_target_lookup *target_map;
const int max_targets;
+ const u32 err_intr_enbl;
+ const u32 err_status_clr;
};
struct tegra234_cbb {
@@ -177,7 +179,7 @@ static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb)
void __iomem *addr;
addr = priv->regs + priv->fabric->notifier_offset;
- writel(0x1ff, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);
+ writel(priv->fabric->err_intr_enbl, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);
dsb(sy);
}
@@ -187,7 +189,7 @@ static void tegra234_cbb_error_clear(struct tegra_cbb *cbb)
writel(0, priv->mon + FABRIC_MN_INITIATOR_ERR_FORCE_0);
- writel(0x3f, priv->mon + FABRIC_MN_INITIATOR_ERR_STATUS_0);
+ writel(priv->fabric->err_status_clr, priv->mon + FABRIC_MN_INITIATOR_ERR_STATUS_0);
dsb(sy);
}
@@ -709,6 +711,8 @@ static const struct tegra234_cbb_fabric tegra234_aon_fabric = {
.max_targets = ARRAY_SIZE(tegra234_aon_target_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
+ .err_intr_enbl = 0x7,
+ .err_status_clr = 0x3f,
.notifier_offset = 0x17000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8d0,
@@ -730,6 +734,8 @@ static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = {
.max_targets = ARRAY_SIZE(tegra234_bpmp_target_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
+ .err_intr_enbl = 0xf,
+ .err_status_clr = 0x3f,
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8f0,
@@ -807,6 +813,8 @@ static const struct tegra234_cbb_fabric tegra234_cbb_fabric = {
.max_targets = ARRAY_SIZE(tegra234_cbb_target_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
+ .err_intr_enbl = 0x7f,
+ .err_status_clr = 0x3f,
.notifier_offset = 0x60000,
.off_mask_erd = 0x3a004,
.firewall_base = 0x10000,
@@ -830,6 +838,8 @@ static const struct tegra234_cbb_fabric tegra234_dce_fabric = {
.max_targets = ARRAY_SIZE(tegra234_common_target_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
+ .err_intr_enbl = 0xf,
+ .err_status_clr = 0x3f,
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x290,
@@ -843,6 +853,8 @@ static const struct tegra234_cbb_fabric tegra234_rce_fabric = {
.max_targets = ARRAY_SIZE(tegra234_common_target_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
+ .err_intr_enbl = 0xf,
+ .err_status_clr = 0x3f,
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x290,
@@ -856,6 +868,8 @@ static const struct tegra234_cbb_fabric tegra234_sce_fabric = {
.max_targets = ARRAY_SIZE(tegra234_common_target_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
+ .err_intr_enbl = 0xf,
+ .err_status_clr = 0x3f,
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x290,
@@ -1040,6 +1054,8 @@ static const struct tegra234_cbb_fabric tegra241_cbb_fabric = {
.max_targets = ARRAY_SIZE(tegra241_cbb_target_map),
.errors = tegra241_cbb_errors,
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
+ .err_intr_enbl = 0x7,
+ .err_status_clr = 0x1ff007f,
.notifier_offset = 0x60000,
.off_mask_erd = 0x40004,
.firewall_base = 0x20000,
@@ -1065,6 +1081,8 @@ static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = {
.max_targets = ARRAY_SIZE(tegra241_bpmp_target_map),
.errors = tegra241_cbb_errors,
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
+ .err_intr_enbl = 0xf,
+ .err_status_clr = 0x1ff007f,
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8f0,
--
2.25.1
next prev parent reply other threads:[~2025-05-30 13:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-30 13:33 [Patch 0/8] Support for Tegra264 and GB10 in CBB driver Sumit Gupta
2025-05-30 13:33 ` [Patch 1/8] soc: tegra: cbb: clear err force register with err status Sumit Gupta
2025-05-30 13:33 ` [Patch 2/8] soc: tegra: cbb: change master-slave to initiator-target Sumit Gupta
2025-05-30 13:33 ` Sumit Gupta [this message]
2025-05-30 13:33 ` [Patch 4/8] soc: tegra: cbb: improve handling for per SoC fabric data Sumit Gupta
2025-05-30 13:33 ` [Patch 5/8] soc: tegra: cbb: support hw lookup to get timed out target address Sumit Gupta
2025-05-30 13:33 ` [Patch 6/8] dt-bindings: arm: tegra: Add NVIDIA Tegra264 CBB 2.0 binding Sumit Gupta
2025-06-03 7:09 ` Krzysztof Kozlowski
2025-05-30 13:33 ` [Patch 7/8] soc: tegra: cbb: add support for cbb fabrics in Tegra264 Sumit Gupta
2025-05-30 13:33 ` [Patch 8/8] soc: tegra: cbb: add support for cbb fabrics in GB10 Sumit Gupta
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