From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C336D1993BD for ; Mon, 2 Jun 2025 06:08:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748844517; cv=none; b=MCE0ZqHmBAb/BkZkAjtIHBFaYgvZww2g/Z7HhFtksO9hynEIyMkAZIL6rpEFD/VaKoSFKXWgw5rzjyH8fJa+pLRx3wYPxQ0ycX4M8NZud9A3kbcrYLD/GoW969JC3vEVyOzrKxA7821gZjqrLPmt0W2QxpLqXyKr61ldDx1lxII= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748844517; c=relaxed/simple; bh=nm54TMUcRYIAPqYH3hllnzIl0n9PJUYqWR00cVuBRxU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZNHAuMmBYE20cP5TR37VxvyR9/Ov9Yv7dS96ERs4IFD7gWQ+taB9ArVqI4GPA2JPfUcQfKH+yXYrpyFFS/YSnpVyoFyA8M4VZtD3jsSqyz4J+ZQ4UJg+hdvAgdYyXN7oov3Oe3cUFMH2tqhEQ58sXVZw9WvvUDNooWN4DS5bMZU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 552684It096309 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 2 Jun 2025 14:08:04 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 2 Jun 2025 14:08:04 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v5 8/8] riscv: defconfig: enable Andes SoC Date: Mon, 2 Jun 2025 14:07:47 +0800 Message-ID: <20250602060747.689824-9-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250602060747.689824-1-ben717@andestech.com> References: <20250602060747.689824-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 552684It096309 Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 3c8e16d71e17..c9214635fb2f 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=y +CONFIG_ARCH_ANDES=y CONFIG_ARCH_MICROCHIP=y CONFIG_ARCH_SIFIVE=y CONFIG_ARCH_SOPHGO=y -- 2.34.1