Re: [PATCH v1 3/7] dt-bindings: interrupt-controller: add generic Risc-v aclint-sswi

[Conor Dooley <conor@kernel.org>]

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On Mon, Jun 09, 2025 at 04:47:45PM +0300, Vladimir Kondratiev wrote:
> Add generic, Risc-V spec compliant (see [1]) aclint-sswi binding
> 
> Thead specific binding preserved, and converted to variant of the
> generic aclint-sswi
> 
> Link: https://github.com/riscvarchive/riscv-aclint [1]

What is the ratification status of this spec?

> 
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
> ---
>  .../riscv,aclint-sswi.yaml                    | 89 +++++++++++++++++++
>  .../thead,c900-aclint-sswi.yaml               | 58 ------------
>  2 files changed, 89 insertions(+), 58 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-sswi.yaml
>  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-sswi.yaml
> new file mode 100644
> index 000000000000..cffddfcfcfea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-sswi.yaml
> @@ -0,0 +1,89 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-sswi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Risc-V ACLINT Supervisor-level Software Interrupt Device

s/Risc-V/RISC-V/g

> +
> +maintainers:
> +  - Inochi Amaoto <inochiama@outlook.com>
> +
> +description:
> +  The SSWI device is a part of the Risc-V ACLINT device. It provides
> +  supervisor-level IPI functionality for a set of HARTs on a THEAD
> +  platform. It provides a register to set an IPI (SETSSIP) for each
> +  HART connected to the SSWI device. See specification
> +  https://github.com/riscvarchive/riscv-aclint
> +
> +  T-HEAD C900 ACLINT is a variant of the ACLINT, using dedicated
> +  compatible string
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - sophgo,sg2044-aclint-sswi
> +          - const: thead,c900-aclint-sswi
> +      - items:
> +          - const: riscv,aclint-sswi

You need a specific compatible for your implementation.
Whether or not this compatible is viable depends on the answer to the
ratification status and/or plan for the spec.

> +
> +  reg:
> +    maxItems: 1
> +
> +  "#interrupt-cells":
> +    const: 0
> +
> +  interrupt-controller: true
> +
> +  interrupts-extended:
> +    minItems: 1
> +    maxItems: 4095
> +
> +  riscv,hart-indexes:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    minItems: 1
> +    maxItems: 16384

maxItems is 4x what is allowed for interrupts-extended. Why?

> +    description:
> +      A list of hart indexes that APLIC should use to address each hart
> +      that is mentioned in the "interrupts-extended"

Please constrain this property to only be permitted on !thead.

> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#interrupt-cells"
> +  - interrupt-controller
> +  - interrupts-extended
> +
> +examples:
> +  - |
> +    //Example 1
> +    interrupt-controller@94000000 {
> +      compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
> +      reg = <0x94000000 0x00004000>;
> +      #interrupt-cells = <0>;
> +      interrupt-controller;
> +      interrupts-extended = <&cpu1intc 1>,
> +                            <&cpu2intc 1>,
> +                            <&cpu3intc 1>,
> +                            <&cpu4intc 1>;
> +    };
> +
> +  - |
> +    //Example 2
> +    interrupt-controller@94000000 {
> +      compatible = "riscv,aclint-sswi";
> +      reg = <0x94000000 0x00004000>;
> +      #interrupt-cells = <0>;
> +      interrupt-controller;
> +      interrupts-extended = <&cpu1intc 1>,
> +                            <&cpu2intc 1>,
> +                            <&cpu3intc 1>,
> +                            <&cpu4intc 1>;
> +      riscv,hart-indexes = <0 1 0x10 0x11>;

Please be consistent. Hex or decimal, but not both.

Cheers,
Conor.

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