From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A8829A9F9; Tue, 10 Jun 2025 12:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749558829; cv=pass; b=Ne86769+fzIC0rmGQSCEmS+uPWTPGZnYhtXGXFayvfsZ3oppgINacUHt30FW7vXZwb16fYMf2KEI1Y+xAjs9Hm//PcDaDOHR8HBE2Xjl7Jz+V0QYDURmSKudeLX7UvT13Gksem+7AUw9GBpfr6ZCS4sd/qAO3l7e8wRHm1fHVTQ= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749558829; c=relaxed/simple; bh=t9viSWGdCUsetfJpuZXGAiDLYQfdL/8Vs7cSbUINsf4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KyOgBumDRkGHeMQcokYPTxT1/d6g/JYPil8wlaNSsVzdOB6Xmin5VOhXeMv8fEyms7dd0FJqKBP3rXC625bstEytPpOvMqq/VUcQNtiil7WC9hJ5dYMgeQyJdF+m9OUz7u46SaVioEjFfLTRD/mIXwcqRekX+fi0OQ4zJr5YIE4= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=W0/9qBAL; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="W0/9qBAL" ARC-Seal: i=1; a=rsa-sha256; t=1749558800; cv=none; d=zohomail.com; s=zohoarc; b=KbETfOGiZH37xLuUpi6vn8QuiB/V4pokvPC0Ot+3pQky05cYm3c8lXBexPKI/5EJZfSSaaB87zOMY+Y2VYo3EGdHSHXJJILp6RZZle9Im3mkyzCsnxMUH6ZQT5DU9mEbN2dmj89fIfNud7gfDNGD25Rxsay3jfPbBpzwJZjBKag= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1749558800; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=um6+orYZmvWyjIKPMULKaYcq3cJ+8tX54fBBdRjWSS4=; b=WaisFqSs5i/OiwKTdC0UVe5P3Uwu29gpu+iQy42U9l6WmR6XXRiaWE4kpfdslPZN61ArPZxQQXcMvPsSl0UizXUKxcmsRdoE3E2O2vOtPFea1uMjFVAghVXT2gd9RiFxmfEWRaCrT6uOt5CZNVCNq4eWCAeSVGWmNYvonAnxZQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1749558799; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=um6+orYZmvWyjIKPMULKaYcq3cJ+8tX54fBBdRjWSS4=; b=W0/9qBAL+3hppBxV14yeK/+YXV9ZLHBdKRb1IcsGBA7q/OdEWF51zA3ektCeiYGJ A7KcbEuelECBy6fus3Q64ZJVF0Rmrfa+Lu6PsO43vd+494aTq7xnAPVNEpSFF3sVR8U Qsa68HZvAeWbF9+JwfzSeRqkZxOR1A57QLNkBOT0= Received: by mx.zohomail.com with SMTPS id 1749558797642874.6088758885295; Tue, 10 Jun 2025 05:33:17 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 10 Jun 2025 14:32:43 +0200 Subject: [PATCH v6 7/7] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250610-rk3576-tsadc-upstream-v6-7-b6e9efbf1015@collabora.com> References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> To: Alexey Charkov , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Thanks to Heiko's work getting OTP working on the RK3576, we can specify the thermal sensor trim values which are stored there now, and with my driver addition to rockchip_thermal, we can make use of these. Add them to the devicetree for the SoC. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index dbc527ec60cfac0bbdb881a27d3ff765366be99e..c388fbb510ade0f06e64c1025dcfa59b8187bc97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1919,6 +1919,30 @@ gpu_leakage: gpu-leakage@21 { log_leakage: log-leakage@22 { reg = <0x22 0x1>; }; + bigcore_tsadc_trim: bigcore-tsadc-trim@24 { + reg = <0x24 0x2>; + bits = <0 10>; + }; + litcore_tsadc_trim: litcore-tsadc-trim@26 { + reg = <0x26 0x2>; + bits = <0 10>; + }; + ddr_tsadc_trim: ddr-tsadc-trim@28 { + reg = <0x28 0x2>; + bits = <0 10>; + }; + npu_tsadc_trim: npu-tsadc-trim@2a { + reg = <0x2a 0x2>; + bits = <0 10>; + }; + gpu_tsadc_trim: gpu-tsadc-trim@2c { + reg = <0x2c 0x2>; + bits = <0 10>; + }; + soc_tsadc_trim: soc-tsadc-trim@64 { + reg = <0x64 0x2>; + bits = <0 10>; + }; }; sai0: sai@2a600000 { @@ -2443,6 +2467,39 @@ tsadc: tsadc@2ae70000 { rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells = <1>; + #size-cells = <0>; + + sensor@0 { + reg = <0>; + nvmem-cells = <&soc_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@1 { + reg = <1>; + nvmem-cells = <&bigcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@2 { + reg = <2>; + nvmem-cells = <&litcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@3 { + reg = <3>; + nvmem-cells = <&ddr_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@4 { + reg = <4>; + nvmem-cells = <&npu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@5 { + reg = <5>; + nvmem-cells = <&gpu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; }; i2c9: i2c@2ae80000 { -- 2.49.0