Re: [PATCH v5 0/8] add Voyager board support

[Conor Dooley <conor@kernel.org>]

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+CC Arnd,

On Thu, Jun 12, 2025 at 12:13:16AM +0800, Ben Zong-You Xie wrote:
> On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
> > [EXTERNAL MAIL]
> 
> > Date: Mon, 9 Jun 2025 17:17:50 +0100
> > From: Conor Dooley <conor@kernel.org>
> > To: Ben Zong-You Xie <ben717@andestech.com>
> > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> >  tim609@andestech.com
> > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > 
> > On Mon, Jun 09, 2025 at 05:16:54PM +0100, Conor Dooley wrote:
> > > On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> > > > On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > > > > [EXTERNAL MAIL]
> > > > 
> > > > > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > > > > From: Conor Dooley <conor@kernel.org>
> > > > > To: Ben Zong-You Xie <ben717@andestech.com>
> > > > > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> > > > >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> > > > >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> > > > >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> > > > >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> > > > >  tim609@andestech.com
> > > > > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > > > > 
> > > > > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > > > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > > > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > > > > files for the QiLai SoC and the Voyager board [1].
> > > > > > 
> > > > > > Now only support basic uart drivers to boot up into a basic console. Other
> > > > > > features will be added later.
> > > > > > 
> > > > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > > > > 
> > > > > Ball is in your court now, after rc1 make a tree and get it in
> > > > > linux-next, and then send a pr to soc@kernel.org with this new content.
> > > > > Perhaps the defconfig should go separately, I can take that one if you
> > > > > want.

> > > > Thanks for your guidance on these patches. I will send a PR to
> > > > soc@kernel.org as you suggested.
> > > > 
> > > > For the defconfig patch, I'm happy for you to handle it. Just let me
> > > > know if there's anything specific you'd like me to include.
> > > 
> > > Okay, I picked it up on the basis that you'll send this all to Arnd for
> > > 6.17
> > 
> > Sorry, I think that was really poorly worded. I picked it up on the
> > basis that you're going to send the other patches in the series to Arnd
> > for 6.17.
> 
> According to the SoC maintainer documentation [1], I should send a
> patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
> I think I should not sent a PR to the main SoC maintainer. Is that right?

I think you can send a PR and not worry about it.

> Further, I have two questions about sending a patchset:   
> 1. Should I send v5 or start a new patchset?
> 2. Should I continue excluding the defconfig patch, as we discussed
>    previously? I think it should be included now.

Arnd, you okay with a defconfig in the same branch as the dts/core
bindings for a new platform? I'll happily drop it from by branch if it
can all go as one.


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