From: Inochi Amaoto <inochiama@gmail.com>
To: Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Vinod Koul <vkoul@kernel.org>,
Alexander Sverdlin <alexander.sverdlin@gmail.com>,
Yu Yuan <yu.yuan@sjtu.edu.cn>, Ze Huang <huangze@whut.edu.cn>,
Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Cc: Junhui Liu <junhui.liu@pigmoral.tech>,
devicetree@vger.kernel.org, sophgo@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
dmaengine@vger.kernel.org, Yixun Lan <dlan@gentoo.org>,
Longbin Li <looong.bin@gmail.com>
Subject: [PATCH v3 4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
Date: Wed, 11 Jun 2025 15:53:18 +0800 [thread overview]
Message-ID: <20250611075321.1160973-5-inochiama@gmail.com> (raw)
In-Reply-To: <20250611075321.1160973-1-inochiama@gmail.com>
Add known reset configuration for existed device.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index 4c3d16764131..e91bb512b099 100644
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -36,6 +36,7 @@ gpio0: gpio@3020000 {
reg = <0x3020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -54,6 +55,7 @@ gpio1: gpio@3021000 {
reg = <0x3021000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO1>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -72,6 +74,7 @@ gpio2: gpio@3022000 {
reg = <0x3022000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO2>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -90,6 +93,7 @@ gpio3: gpio@3023000 {
reg = <0x3023000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO3>;
portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -133,6 +137,7 @@ i2c0: i2c@4000000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C0>;
status = "disabled";
};
@@ -144,6 +149,7 @@ i2c1: i2c@4010000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C1>;
status = "disabled";
};
@@ -155,6 +161,7 @@ i2c2: i2c@4020000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C2>;
status = "disabled";
};
@@ -166,6 +173,7 @@ i2c3: i2c@4030000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C3>;
status = "disabled";
};
@@ -177,6 +185,7 @@ i2c4: i2c@4040000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C4>;
status = "disabled";
};
@@ -188,6 +197,7 @@ uart0: serial@4140000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART0>;
status = "disabled";
};
@@ -199,6 +209,7 @@ uart1: serial@4150000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART1>;
status = "disabled";
};
@@ -210,6 +221,7 @@ uart2: serial@4160000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART2>;
status = "disabled";
};
@@ -221,6 +233,7 @@ uart3: serial@4170000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART3>;
status = "disabled";
};
@@ -232,6 +245,7 @@ spi0: spi@4180000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI0>;
status = "disabled";
};
@@ -243,6 +257,7 @@ spi1: spi@4190000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI1>;
status = "disabled";
};
@@ -254,6 +269,7 @@ spi2: spi@41a0000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI2>;
status = "disabled";
};
@@ -265,6 +281,7 @@ spi3: spi@41b0000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI3>;
status = "disabled";
};
@@ -276,6 +293,7 @@ uart4: serial@41c0000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART4>;
status = "disabled";
};
--
2.49.0
prev parent reply other threads:[~2025-06-11 7:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-11 7:53 [PATCH v3 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
2025-06-11 7:53 ` [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support Inochi Amaoto
2025-06-11 8:19 ` Krzysztof Kozlowski
2025-06-11 8:21 ` Krzysztof Kozlowski
2025-06-11 8:23 ` Inochi Amaoto
2025-06-11 8:29 ` Inochi Amaoto
2025-06-11 9:09 ` Krzysztof Kozlowski
2025-06-11 9:45 ` Inochi Amaoto
2025-06-11 7:53 ` [PATCH v3 2/4] reset: simple: add support for Sophgo CV1800B Inochi Amaoto
2025-06-15 15:39 ` Alexander Sverdlin
2025-06-11 7:53 ` [PATCH v3 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
2025-06-11 10:07 ` Junhui Liu
2025-06-15 15:39 ` Alexander Sverdlin
2025-06-11 7:53 ` Inochi Amaoto [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250611075321.1160973-5-inochiama@gmail.com \
--to=inochiama@gmail.com \
--cc=alex@ghiti.fr \
--cc=alexander.sverdlin@gmail.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dlan@gentoo.org \
--cc=dmaengine@vger.kernel.org \
--cc=huangze@whut.edu.cn \
--cc=junhui.liu@pigmoral.tech \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=looong.bin@gmail.com \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh@kernel.org \
--cc=sophgo@lists.linux.dev \
--cc=thomas.bonnefille@bootlin.com \
--cc=unicorn_wang@outlook.com \
--cc=vkoul@kernel.org \
--cc=yu.yuan@sjtu.edu.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox