[PATCH RFC 0/7] i3c: add driver for the Renesas IP and support RZ/G3S+G3E

[PATCH RFC 0/7] i3c: add driver for the Renesas IP and support RZ/G3S+G3E

[Wolfram Sang]

Here is finally the first RFC of a driver for the Renesas I3C IP. It was
created by merging two versions of it from two different BSPs. Then,
improved according to code analyzers, cleaned up with regard to coding
style, and then refactored to hopefully match I3C subsystem standards.

It is a basic driver for the I3C IP found in various SoCs like RZ/G3S
and G3E. Missing features to be added incrementally are IBI, HotJoin and
maybe target support. Other than that, this driver has been tested with
I3C pure busses (2 targets) and mixed busses (2 I3C + various I2C
targets). DAA and reading/writing to the temperature sensors worked
reliably at different speeds. Scoping the bus, the output from the
protocol analyzer seems reasonable, too. But hey, I am still new to all
this, so I might have overlooked something.

The first patches are needed to enable I3C on the RZ/G3S and G3E boards.
Once this series loses RFC status, they will be sent out individually,
of course. All is on top of 6.16-rc1. A branch can be found here:

git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/g3s/i3c

Why is this still RFC?

- On G3E (but not G3S), we get a spurious irq during boot. We are
  working on it. This is just platform dependent, though, kind of
  independent of the high level design of the driver. For this, we
  would love to get comments already. So, we can fix things in parallel

- G3S has 17 irqs, G3E only 16. The way we handle this might need
  discussion (see patch 3)

- On G3S, clocks are named 'i3c' while on G3E they are named 'i3c0'
  I don't have all the needed docs for this, but Tommaso can surely
  figure this out meanwhile

- There are some open questions regarding the driver itself
  (see patch 4)

Really looking forward to comments! This has been quite a ride. Getting
a suitable test setup was a surprisingly big task. If someone knows an
off-the-shelf device supporting HotJoin, I am all ears. I couldn't find
one.

So much for now here, some patches have more details.

All the best,

   Wolfram


Quynh Nguyen (1):
  arm64: dts: renesas: r9a08g045: Add I3C node

Tommaso Merciai (3):
  clk: renesas: r9a09g047: Add I3C0 clocks and resets
  dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller
  arm64: dts: renesas: r9a09g047: Add I3C node

Wolfram Sang (3):
  clk: renesas: r9a08g045: Add I3C clocks, resets and power domain
  i3c: add driver for Renesas I3C IP
  WIP: arm64: dts: renesas: rzg3s-smarc-som: Enable I3C

 .../devicetree/bindings/i3c/renesas,i3c.yaml  |  186 +++
 MAINTAINERS                                   |    7 +
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |   35 +
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |   35 +
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |   33 +
 drivers/clk/renesas/r9a08g045-cpg.c           |    7 +
 drivers/clk/renesas/r9a09g047-cpg.c           |    8 +
 drivers/i3c/master/Kconfig                    |   10 +
 drivers/i3c/master/Makefile                   |    1 +
 drivers/i3c/master/renesas-i3c.c              | 1441 +++++++++++++++++
 10 files changed, 1763 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
 create mode 100644 drivers/i3c/master/renesas-i3c.c

-- 
2.47.2

[PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Wolfram Sang]

From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Available in RZ/G3S and G3E SoCs. The G3S has 17 interrupts, the G3E 16
with the "HDR exit" interrupt missing. This interrupt is put to the end
of the list, so we can handle the difference using "minItems" instead of
defining a separate interrupt list per SoC.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Tommaso also did a version with two interrupt lists and using 'oneOf'. I
prefer this version but maybe the other one is preferred upstream?

 .../devicetree/bindings/i3c/renesas,i3c.yaml  | 186 ++++++++++++++++++
 1 file changed, 186 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml

diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
new file mode 100644
index 000000000000..e6e6c57bb56c
--- /dev/null
+++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
@@ -0,0 +1,186 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas I3C Bus Interface
+
+maintainers:
+  - Wolfram Sang <wsa+renesas@sang-engineering.com>
+  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a08g045-i3c # RZ/G3S
+          - renesas,r9a09g047-i3c # RZ/G3E
+      - const: renesas,i3c
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Non-recoverable internal error interrupt
+      - description: Normal transfer error interrupt
+      - description: Normal transfer abort interrupt
+      - description: Normal response status buffer full interrupt
+      - description: Normal command buffer empty interrupt
+      - description: Normal IBI status buffer full interrupt
+      - description: Normal Rx data buffer full interrupt
+      - description: Normal Tx data buffer empty interrupt
+      - description: Normal receive status buffer full interrupt
+      - description: START condition detection interrupt
+      - description: STOP condition detection interrupt
+      - description: Transmit end interrupt
+      - description: NACK detection interrupt
+      - description: Arbitration lost interrupt
+      - description: Timeout detection interrupt
+      - description: Wake-up condition detection interrupt
+      - description: HDR Exit Pattern detection interrupt
+    minItems: 16
+
+  interrupt-names:
+    items:
+      - const: ierr
+      - const: terr
+      - const: abort
+      - const: resp
+      - const: cmd
+      - const: ibi
+      - const: rx
+      - const: tx
+      - const: rcv
+      - const: st
+      - const: sp
+      - const: tend
+      - const: nack
+      - const: al
+      - const: tmo
+      - const: wu
+      - const: exit
+    minItems: 16
+
+  clocks:
+    oneOf:
+      - items:
+          - description: APB bus clock
+          - description: transfer clock
+      - items:
+          - description: APB bus clock
+          - description: SFRs clock
+          - description: transfer clock
+
+  clock-names:
+    oneOf:
+      - items:
+          - const: pclk
+          - const: tclk
+      - items:
+          - const: pclk
+          - const: pclkrw
+          - const: tclk
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: Reset signal
+      - description: APB interface reset signal/SCAN reset signal
+
+  reset-names:
+    items:
+      - const: presetn
+      - const: tresetn
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clock-names
+  - clocks
+  - power-domains
+  - resets
+  - reset-names
+
+allOf:
+  - $ref: i3c.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g045-i3c
+    then:
+      properties:
+        clocks:
+          maxItems: 2
+        clock-names:
+          maxItems: 2
+        interrupts:
+          minItems: 17
+        interrupt-names:
+          minItems: 17
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g047-i3c
+    then:
+      properties:
+        clocks:
+          minItems: 3
+        clock-names:
+          minItems: 3
+        interrupts:
+          maxItems: 16
+        interrupt-names:
+          maxItems: 16
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a08g045-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    i3c@1005b000 {
+        compatible = "renesas,r9a08g045-i3c", "renesas,i3c";
+        reg = <0x1005b000 0x1000>;
+        clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
+                 <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
+        clock-names = "pclk", "tclk";
+        interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "ierr", "terr", "abort", "resp",
+                          "cmd", "ibi", "rx", "tx", "rcv",
+                          "st", "sp", "tend", "nack",
+                          "al", "tmo", "wu", "exit";
+        resets = <&cpg R9A08G045_I3C_PRESETN>,
+                 <&cpg R9A08G045_I3C_TRESETN>;
+        reset-names = "presetn", "tresetn";
+        power-domains = <&cpg>;
+        #address-cells = <3>;
+        #size-cells = <0>;
+    };
+...
-- 
2.47.2

[PATCH RFC 5/7] arm64: dts: renesas: r9a08g045: Add I3C node

[Wolfram Sang]

From: Quynh Nguyen <quynh.nguyen.xb@renesas.com>

Add I3C node to RZ/G3S SoC DTSI

Signed-off-by: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
[wsa: rebased, moved bus frequencies to board file]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 0364f89776e6..03de06209d3c 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -272,6 +272,41 @@ channel@8 {
 			};
 		};
 
+		i3c: i3c@1005b000 {
+			compatible = "renesas,r9a08g045-i3c", "renesas,i3c";
+			reg = <0 0x1005b000 0 0x1000>;
+			clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
+				 <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
+			clock-names = "pclk", "tclk";
+			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ierr", "terr", "abort", "resp", "cmd",
+					  "ibi", "rx", "tx", "rcv","st", "sp",
+					  "tend", "nack", "al", "tmo", "wu", "exit";
+			resets = <&cpg R9A08G045_I3C_PRESETN>,
+				 <&cpg R9A08G045_I3C_TRESETN>;
+			reset-names = "presetn", "tresetn";
+			power-domains = <&cpg>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		vbattb: clock-controller@1005c000 {
 			compatible = "renesas,r9a08g045-vbattb";
 			reg = <0 0x1005c000 0 0x1000>;
-- 
2.47.2

[PATCH RFC 6/7] arm64: dts: renesas: r9a09g047: Add I3C node

[Wolfram Sang]

From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Add I3C node support.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 876f70fed433..0c0fbddfd7d4 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -580,6 +580,41 @@ i2c8: i2c@11c01000 {
 			status = "disabled";
 		};
 
+		i3c0: i3c@12400000 {
+			compatible = "renesas,r9a09g047-i3c", "renesas,i3c";
+			reg = <0 0x12400000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0x90>,
+				 <&cpg CPG_MOD 0x91>,
+				 <&cpg CPG_MOD 0x92>;
+			clock-names = "pclk", "pclkrw", "tclk";
+			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ierr", "terr", "abort", "resp",
+					  "cmd", "ibi", "rx", "tx", "rcv",
+					  "st", "sp", "tend", "nack", "al",
+					  "tmo", "wu";
+			resets = <&cpg 0x96>, <&cpg 0x97>;
+			reset-names = "presetn", "tresetn";
+			power-domains = <&cpg>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		gpu: gpu@14850000 {
 			compatible = "renesas,r9a09g047-mali",
 				     "arm,mali-bifrost";
-- 
2.47.2

[PATCH RFC 7/7] WIP: arm64: dts: renesas: rzg3s-smarc-som: Enable I3C

[Wolfram Sang]

This is really only for testing. Not for upstream!

Not-signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 39845faec894..f3f391c609d3 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i3c/i3c.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
 #include "rzg3s-smarc-switches.h"
@@ -172,6 +173,38 @@ a0 80 30 30 9c
 	};
 };
 
+#undef I3C_BUS_PURE
+#ifdef I3C_BUS_PURE
+&i3c {
+	i2c-scl-hz = <1000000>;
+	i3c-scl-hz = <2000000>;		/* slow Logic Analyzer here */
+	//i3c-scl-hz = <12500000>;
+	status = "okay";
+};
+#else
+&i3c {
+	i2c-scl-hz = <400000>;		/* Max speed of the ADT7411 below */
+	/*
+	 * 10MHz works somewhat with my 24MHz logic analyzer as well as
+	 * signal width < 50ns for the legacy I2C filters
+	 */
+	i3c-scl-hz = <10000000>;
+	status = "okay";
+
+	/* I2C bus from SMARC via PMOD6A. EEPROM driver only used to verify register content */
+	eeprom@1a {
+		compatible = "atmel,24c02";
+		reg = <0x1a 0 (I2C_FM | I2C_FILTER)>;
+	};
+
+	/* externel development board */
+	temp@4a {
+		compatible = "adi,adt7411";
+		reg = <0x4a 0 (I2C_FM | I2C_FILTER)>;
+	};
+};
+#endif
+
 #if SW_CONFIG2 == SW_ON
 /* SD0 slot */
 &sdhi0 {
-- 
2.47.2

Re: [PATCH RFC 0/7] i3c: add driver for the Renesas IP and support RZ/G3S+G3E

[Rob Herring (Arm)]

On Wed, 11 Jun 2025 11:39:24 +0200, Wolfram Sang wrote:
> Here is finally the first RFC of a driver for the Renesas I3C IP. It was
> created by merging two versions of it from two different BSPs. Then,
> improved according to code analyzers, cleaned up with regard to coding
> style, and then refactored to hopefully match I3C subsystem standards.
> 
> It is a basic driver for the I3C IP found in various SoCs like RZ/G3S
> and G3E. Missing features to be added incrementally are IBI, HotJoin and
> maybe target support. Other than that, this driver has been tested with
> I3C pure busses (2 targets) and mixed busses (2 I3C + various I2C
> targets). DAA and reading/writing to the temperature sensors worked
> reliably at different speeds. Scoping the bus, the output from the
> protocol analyzer seems reasonable, too. But hey, I am still new to all
> this, so I might have overlooked something.
> 
> The first patches are needed to enable I3C on the RZ/G3S and G3E boards.
> Once this series loses RFC status, they will be sent out individually,
> of course. All is on top of 6.16-rc1. A branch can be found here:
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/g3s/i3c
> 
> Why is this still RFC?
> 
> - On G3E (but not G3S), we get a spurious irq during boot. We are
>   working on it. This is just platform dependent, though, kind of
>   independent of the high level design of the driver. For this, we
>   would love to get comments already. So, we can fix things in parallel
> 
> - G3S has 17 irqs, G3E only 16. The way we handle this might need
>   discussion (see patch 3)
> 
> - On G3S, clocks are named 'i3c' while on G3E they are named 'i3c0'
>   I don't have all the needed docs for this, but Tommaso can surely
>   figure this out meanwhile
> 
> - There are some open questions regarding the driver itself
>   (see patch 4)
> 
> Really looking forward to comments! This has been quite a ride. Getting
> a suitable test setup was a surprisingly big task. If someone knows an
> off-the-shelf device supporting HotJoin, I am all ears. I couldn't find
> one.
> 
> So much for now here, some patches have more details.
> 
> All the best,
> 
>    Wolfram
> 
> 
> Quynh Nguyen (1):
>   arm64: dts: renesas: r9a08g045: Add I3C node
> 
> Tommaso Merciai (3):
>   clk: renesas: r9a09g047: Add I3C0 clocks and resets
>   dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller
>   arm64: dts: renesas: r9a09g047: Add I3C node
> 
> Wolfram Sang (3):
>   clk: renesas: r9a08g045: Add I3C clocks, resets and power domain
>   i3c: add driver for Renesas I3C IP
>   WIP: arm64: dts: renesas: rzg3s-smarc-som: Enable I3C
> 
>  .../devicetree/bindings/i3c/renesas,i3c.yaml  |  186 +++
>  MAINTAINERS                                   |    7 +
>  arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |   35 +
>  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |   35 +
>  .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |   33 +
>  drivers/clk/renesas/r9a08g045-cpg.c           |    7 +
>  drivers/clk/renesas/r9a09g047-cpg.c           |    8 +
>  drivers/i3c/master/Kconfig                    |   10 +
>  drivers/i3c/master/Makefile                   |    1 +
>  drivers/i3c/master/renesas-i3c.c              | 1441 +++++++++++++++++
>  10 files changed, 1763 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
>  create mode 100644 drivers/i3c/master/renesas-i3c.c
> 
> --
> 2.47.2
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/v6.16-rc1 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20250611093934.4208-1-wsa+renesas@sang-engineering.com:

arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: /soc/i3c@1005b000/temp@4a: failed to match any schema with compatible: ['adi,adt7411']

Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Frank Li]

On Wed, Jun 11, 2025 at 11:39:27AM +0200, Wolfram Sang wrote:
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>
> Available in RZ/G3S and G3E SoCs. The G3S has 17 interrupts, the G3E 16
> with the "HDR exit" interrupt missing. This interrupt is put to the end
> of the list, so we can handle the difference using "minItems" instead of
> defining a separate interrupt list per SoC.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>
> Tommaso also did a version with two interrupt lists and using 'oneOf'. I
> prefer this version but maybe the other one is preferred upstream?
>
>  .../devicetree/bindings/i3c/renesas,i3c.yaml  | 186 ++++++++++++++++++
>  1 file changed, 186 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
>
> diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
> new file mode 100644
> index 000000000000..e6e6c57bb56c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
> @@ -0,0 +1,186 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas I3C Bus Interface
> +
> +maintainers:
> +  - Wolfram Sang <wsa+renesas@sang-engineering.com>
> +  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,r9a08g045-i3c # RZ/G3S
> +          - renesas,r9a09g047-i3c # RZ/G3E
> +      - const: renesas,i3c
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: Non-recoverable internal error interrupt
> +      - description: Normal transfer error interrupt
> +      - description: Normal transfer abort interrupt
> +      - description: Normal response status buffer full interrupt
> +      - description: Normal command buffer empty interrupt
> +      - description: Normal IBI status buffer full interrupt
> +      - description: Normal Rx data buffer full interrupt
> +      - description: Normal Tx data buffer empty interrupt
> +      - description: Normal receive status buffer full interrupt
> +      - description: START condition detection interrupt
> +      - description: STOP condition detection interrupt
> +      - description: Transmit end interrupt
> +      - description: NACK detection interrupt
> +      - description: Arbitration lost interrupt
> +      - description: Timeout detection interrupt
> +      - description: Wake-up condition detection interrupt
> +      - description: HDR Exit Pattern detection interrupt
> +    minItems: 16
> +
> +  interrupt-names:
> +    items:
> +      - const: ierr
> +      - const: terr
> +      - const: abort
> +      - const: resp
> +      - const: cmd
> +      - const: ibi
> +      - const: rx
> +      - const: tx
> +      - const: rcv
> +      - const: st
> +      - const: sp
> +      - const: tend
> +      - const: nack
> +      - const: al
> +      - const: tmo
> +      - const: wu
> +      - const: exit
> +    minItems: 16
> +
> +  clocks:
> +    oneOf:
> +      - items:
> +          - description: APB bus clock
> +          - description: transfer clock
> +      - items:
> +          - description: APB bus clock
> +          - description: SFRs clock
> +          - description: transfer clock
> +
> +  clock-names:
> +    oneOf:
> +      - items:
> +          - const: pclk
> +          - const: tclk
> +      - items:
> +          - const: pclk
> +          - const: pclkrw
> +          - const: tclk

Suggested clock name is, apb, trans, srfs.
Needn't clk surfix and provide meanful name.

> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    items:
> +      - description: Reset signal
> +      - description: APB interface reset signal/SCAN reset signal
> +
> +  reset-names:
> +    items:
> +      - const: presetn
> +      - const: tresetn

the same here:  per, apb

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clock-names
> +  - clocks
> +  - power-domains
> +  - resets
> +  - reset-names
> +
> +allOf:
> +  - $ref: i3c.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a08g045-i3c
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 2
> +        clock-names:
> +          maxItems: 2
> +        interrupts:
> +          minItems: 17
> +        interrupt-names:
> +          minItems: 17
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g047-i3c
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 3
> +        clock-names:
> +          minItems: 3
> +        interrupts:
> +          maxItems: 16
> +        interrupt-names:
> +          maxItems: 16
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    i3c@1005b000 {
> +        compatible = "renesas,r9a08g045-i3c", "renesas,i3c";
> +        reg = <0x1005b000 0x1000>;
> +        clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
> +                 <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
> +        clock-names = "pclk", "tclk";
> +        interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "ierr", "terr", "abort", "resp",
> +                          "cmd", "ibi", "rx", "tx", "rcv",
> +                          "st", "sp", "tend", "nack",
> +                          "al", "tmo", "wu", "exit";
> +        resets = <&cpg R9A08G045_I3C_PRESETN>,
> +                 <&cpg R9A08G045_I3C_TRESETN>;
> +        reset-names = "presetn", "tresetn";
> +        power-domains = <&cpg>;
> +        #address-cells = <3>;
> +        #size-cells = <0>;

I prefer put #address-cells and #size-cells after reg

Frank
> +    };
> +...
> --
> 2.47.2
>

Re: [PATCH RFC 0/7] i3c: add driver for the Renesas IP and support RZ/G3S+G3E

[Wolfram Sang]

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> New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20250611093934.4208-1-wsa+renesas@sang-engineering.com:
> 
> arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: /soc/i3c@1005b000/temp@4a: failed to match any schema with compatible: ['adi,adt7411']

I sent a patch for 'trivial-devices' to fix this already [1]. I forgot
to add it to this series, sorry.

[1] https://lore.kernel.org/r/20250608162240.3023-2-wsa+renesas@sang-engineering.com


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Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Wolfram Sang]

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Hi Frank,

> > +  clock-names:
> > +    oneOf:
> > +      - items:
> > +          - const: pclk
> > +          - const: tclk
> > +      - items:
> > +          - const: pclk
> > +          - const: pclkrw
> > +          - const: tclk
> 
> Suggested clock name is, apb, trans, srfs.
> Needn't clk surfix and provide meanful name.

? Why can't we have the name from the datasheets? It will be
unnecessarily hard for users to verify the correctness of the clock
assignments if they need an artifical mapping of these names. If they
are the same as in the datasheet, the same task becomes very easy.


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Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Tommaso Merciai]

Hi Frank, Wolfram,

Thanks both for your work.

On 12/06/25 16:31, Wolfram Sang wrote:
> Hi Frank,
> 
>>> +  clock-names:
>>> +    oneOf:
>>> +      - items:
>>> +          - const: pclk
>>> +          - const: tclk
>>> +      - items:
>>> +          - const: pclk
>>> +          - const: pclkrw
>>> +          - const: tclk
>>
>> Suggested clock name is, apb, trans, srfs.
>> Needn't clk surfix and provide meanful name.
> 
> ? Why can't we have the name from the datasheets? It will be
> unnecessarily hard for users to verify the correctness of the clock
> assignments if they need an artifical mapping of these names. If they
> are the same as in the datasheet, the same task becomes very easy.
> 

Agreed.
Since the name comes from the hw manual I think is better to leave it as is.

Thanks & Regards,
Tommaso

Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Frank Li]

On Thu, Jun 12, 2025 at 04:51:42PM +0200, Tommaso Merciai wrote:
> Hi Frank, Wolfram,
>
> Thanks both for your work.
>
> On 12/06/25 16:31, Wolfram Sang wrote:
> > Hi Frank,
> >
> > > > +  clock-names:
> > > > +    oneOf:
> > > > +      - items:
> > > > +          - const: pclk
> > > > +          - const: tclk
> > > > +      - items:
> > > > +          - const: pclk
> > > > +          - const: pclkrw
> > > > +          - const: tclk
> > >
> > > Suggested clock name is, apb, trans, srfs.
> > > Needn't clk surfix and provide meanful name.
> >
> > ? Why can't we have the name from the datasheets? It will be
> > unnecessarily hard for users to verify the correctness of the clock
> > assignments if they need an artifical mapping of these names. If they
> > are the same as in the datasheet, the same task becomes very easy.
> >
>
> Agreed.
> Since the name comes from the hw manual I think is better to leave it as is.

Previous Krzysztof give some feedback about clock-names, they don't perfer
clk surfix, because clock-names already provide information, which is clock.

Some hardware manual use it as signal name, for example, pclk which is apb
bus clock.

I am fine with align signal name. you can wait for DT team's feedback about
this.

Frank


>
> Thanks & Regards,
> Tommaso

Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Rob Herring]

On Thu, Jun 12, 2025 at 04:51:42PM +0200, Tommaso Merciai wrote:
> Hi Frank, Wolfram,
> 
> Thanks both for your work.
> 
> On 12/06/25 16:31, Wolfram Sang wrote:
> > Hi Frank,
> > 
> > > > +  clock-names:
> > > > +    oneOf:
> > > > +      - items:
> > > > +          - const: pclk
> > > > +          - const: tclk
> > > > +      - items:
> > > > +          - const: pclk
> > > > +          - const: pclkrw
> > > > +          - const: tclk
> > > 
> > > Suggested clock name is, apb, trans, srfs.

Suggested by who?

> > > Needn't clk surfix and provide meanful name.
> > 
> > ? Why can't we have the name from the datasheets? It will be
> > unnecessarily hard for users to verify the correctness of the clock
> > assignments if they need an artifical mapping of these names. If they
> > are the same as in the datasheet, the same task becomes very easy.
> > 
> 
> Agreed.
> Since the name comes from the hw manual I think is better to leave it as is.

Agreed.

While 'clk' is considered redundant, naming clocks 'p' and 't' is too 
terse even for me. So the rule is clk is redundant unless it is with a 
single letter. The rules apply to s/w folks making up names, not h/w 
manuals.

Rob

Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Rob Herring]

On Wed, Jun 11, 2025 at 11:39:27AM +0200, Wolfram Sang wrote:
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> 
> Available in RZ/G3S and G3E SoCs. The G3S has 17 interrupts, the G3E 16
> with the "HDR exit" interrupt missing. This interrupt is put to the end
> of the list, so we can handle the difference using "minItems" instead of
> defining a separate interrupt list per SoC.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
> 
> Tommaso also did a version with two interrupt lists and using 'oneOf'. I
> prefer this version but maybe the other one is preferred upstream?
> 
>  .../devicetree/bindings/i3c/renesas,i3c.yaml  | 186 ++++++++++++++++++
>  1 file changed, 186 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
> 
> diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
> new file mode 100644
> index 000000000000..e6e6c57bb56c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
> @@ -0,0 +1,186 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas I3C Bus Interface
> +
> +maintainers:
> +  - Wolfram Sang <wsa+renesas@sang-engineering.com>
> +  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,r9a08g045-i3c # RZ/G3S
> +          - renesas,r9a09g047-i3c # RZ/G3E
> +      - const: renesas,i3c
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: Non-recoverable internal error interrupt
> +      - description: Normal transfer error interrupt
> +      - description: Normal transfer abort interrupt
> +      - description: Normal response status buffer full interrupt
> +      - description: Normal command buffer empty interrupt
> +      - description: Normal IBI status buffer full interrupt
> +      - description: Normal Rx data buffer full interrupt
> +      - description: Normal Tx data buffer empty interrupt
> +      - description: Normal receive status buffer full interrupt
> +      - description: START condition detection interrupt
> +      - description: STOP condition detection interrupt
> +      - description: Transmit end interrupt
> +      - description: NACK detection interrupt
> +      - description: Arbitration lost interrupt
> +      - description: Timeout detection interrupt
> +      - description: Wake-up condition detection interrupt
> +      - description: HDR Exit Pattern detection interrupt
> +    minItems: 16
> +
> +  interrupt-names:
> +    items:
> +      - const: ierr
> +      - const: terr
> +      - const: abort
> +      - const: resp
> +      - const: cmd
> +      - const: ibi
> +      - const: rx
> +      - const: tx
> +      - const: rcv
> +      - const: st
> +      - const: sp
> +      - const: tend
> +      - const: nack
> +      - const: al
> +      - const: tmo
> +      - const: wu
> +      - const: exit
> +    minItems: 16
> +
> +  clocks:
> +    oneOf:
> +      - items:
> +          - description: APB bus clock
> +          - description: transfer clock
> +      - items:
> +          - description: APB bus clock
> +          - description: SFRs clock
> +          - description: transfer clock

It's a new binding, why don't you put SFRs clock last and simplify the 
schema?

> +
> +  clock-names:
> +    oneOf:
> +      - items:
> +          - const: pclk
> +          - const: tclk
> +      - items:
> +          - const: pclk
> +          - const: pclkrw
> +          - const: tclk

Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Frank Li]

On Wed, Jun 25, 2025 at 03:04:51PM -0500, Rob Herring wrote:
> On Thu, Jun 12, 2025 at 04:51:42PM +0200, Tommaso Merciai wrote:
> > Hi Frank, Wolfram,
> >
> > Thanks both for your work.
> >
> > On 12/06/25 16:31, Wolfram Sang wrote:
> > > Hi Frank,
> > >
> > > > > +  clock-names:
> > > > > +    oneOf:
> > > > > +      - items:
> > > > > +          - const: pclk
> > > > > +          - const: tclk
> > > > > +      - items:
> > > > > +          - const: pclk
> > > > > +          - const: pclkrw
> > > > > +          - const: tclk
> > > >
> > > > Suggested clock name is, apb, trans, srfs.
>
> Suggested by who?

It is my suggestion base on
 - 1: needn't clk surfix. But you provide rule below.
 - 2: pclk, tclk ... can't provide any meansful information to user.
It is hard to know what's that without check binding doc. And most case
there are not description under clocks.

but some common clock-names term for IP, like apb, bus, which will be easy
to know apb (control access register). 'bus' feed into i3c bus clock speed.
'bus' is important for i3c to set 12Mhz or lower freqeuncy for old i2c
devices.

Frank


>
> > > > Needn't clk surfix and provide meanful name.
> > >
> > > ? Why can't we have the name from the datasheets? It will be
> > > unnecessarily hard for users to verify the correctness of the clock
> > > assignments if they need an artifical mapping of these names. If they
> > > are the same as in the datasheet, the same task becomes very easy.
> > >
> >
> > Agreed.
> > Since the name comes from the hw manual I think is better to leave it as is.
>
> Agreed.
>
> While 'clk' is considered redundant, naming clocks 'p' and 't' is too
> terse even for me. So the rule is clk is redundant unless it is with a
> single letter. The rules apply to s/w folks making up names, not h/w
> manuals.
>
> Rob
>
> --
> linux-i3c mailing list
> linux-i3c@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-i3c

Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Wolfram Sang]

> > +  interrupt-names:
> > +    items:
> > +      - const: ierr
> > +      - const: terr
> > +      - const: abort
> > +      - const: resp
> > +      - const: cmd
> > +      - const: ibi
> > +      - const: rx
> > +      - const: tx
> > +      - const: rcv
> > +      - const: st
> > +      - const: sp
> > +      - const: tend
> > +      - const: nack
> > +      - const: al
> > +      - const: tmo
> > +      - const: wu
> > +      - const: exit
> > +    minItems: 16
> > +
> > +  clocks:
> > +    oneOf:
> > +      - items:
> > +          - description: APB bus clock
> > +          - description: transfer clock
> > +      - items:
> > +          - description: APB bus clock
> > +          - description: SFRs clock
> > +          - description: transfer clock
> 
> It's a new binding, why don't you put SFRs clock last and simplify the 
> schema?

Similar how we handle interrupts? 16 for the one SoC, 17 for the other?
Putting the optional entry to the end of the array? Tommaso, can you
integrate this change, please?

Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Tommaso Merciai]

Hi Wolfram, Rob,

On 30/06/25 21:43, Wolfram Sang wrote:
> 
>>> +  interrupt-names:
>>> +    items:
>>> +      - const: ierr
>>> +      - const: terr
>>> +      - const: abort
>>> +      - const: resp
>>> +      - const: cmd
>>> +      - const: ibi
>>> +      - const: rx
>>> +      - const: tx
>>> +      - const: rcv
>>> +      - const: st
>>> +      - const: sp
>>> +      - const: tend
>>> +      - const: nack
>>> +      - const: al
>>> +      - const: tmo
>>> +      - const: wu
>>> +      - const: exit
>>> +    minItems: 16
>>> +
>>> +  clocks:
>>> +    oneOf:
>>> +      - items:
>>> +          - description: APB bus clock
>>> +          - description: transfer clock
>>> +      - items:
>>> +          - description: APB bus clock
>>> +          - description: SFRs clock
>>> +          - description: transfer clock
>>
>> It's a new binding, why don't you put SFRs clock last and simplify the
>> schema?
> 
> Similar how we handle interrupts? 16 for the one SoC, 17 for the other?
> Putting the optional entry to the end of the array? Tommaso, can you
> integrate this change, please?
> 

   clocks:
     items:
       - description: APB bus clock
       - description: transfer clock
       - description: SFRs clock
     minItems: 2

   clock-names:
     items:
       - const: pclk
       - const: tclk
       - const: pclkrw
     minItems: 2

...

allOf:
   - $ref: i3c.yaml#

   - if:
       properties:
         compatible:
           contains:
             const: renesas,r9a08g045-i3c
     then:
       properties:
         clocks:
           maxItems: 2
         clock-names:
           maxItems: 2
         interrupts:
           minItems: 17
         interrupt-names:
           minItems: 17

   - if:
       properties:
         compatible:
           contains:
             const: renesas,r9a09g047-i3c
     then:
       properties:
         clocks:
           minItems: 3
         clock-names:
           minItems: 3
         interrupts:
           maxItems: 16
         interrupt-names:
           maxItems: 16

Right?
Please correct me if I'm missing somenthing.
Thanks in advance.

Thanks & Regards,
Tommaso

Re: [PATCH RFC 3/7] dt-bindings: i3c: renesas,i3c: Add binding for Renesas I3C controller

[Wolfram Sang]

...

>   - if:
>       properties:
>         compatible:
>           contains:
>             const: renesas,r9a09g047-i3c
>     then:
>       properties:
>         clocks:
>           minItems: 3
>         clock-names:
>           minItems: 3
>         interrupts:
>           maxItems: 16
>         interrupt-names:
>           maxItems: 16
> 
> Right?
> Please correct me if I'm missing somenthing.

LGTM. I will send it out like this in the v1 version.