* [PATCH v5] dt-bindings: net: Convert socfpga-dwmac bindings to yaml
@ 2025-06-12 22:16 Matthew Gerlach
2025-06-13 6:14 ` Maxime Chevallier
2025-06-13 12:11 ` kernel test robot
0 siblings, 2 replies; 3+ messages in thread
From: Matthew Gerlach @ 2025-06-12 22:16 UTC (permalink / raw)
To: andrew+netdev, davem, edumazet, kuba, pabeni, robh, krzk+dt,
conor+dt, maxime.chevallier, mcoquelin.stm32, alexandre.torgue,
richardcochran, netdev, devicetree, linux-kernel, linux-stm32,
linux-arm-kernel
Cc: Matthew Gerlach, Mun Yew Tham
Convert the bindings for socfpga-dwmac to yaml. Since the original
text contained descriptions for two separate nodes, two separate
yaml files were created.
Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
v5:
- Fix dt_binding_check error: comptabile.
- Rename altr,gmii-to-sgmii.yaml to altr,gmii-to-sgmii-2.0.yaml
v4:
- Change filename from socfpga,dwmac.yaml to altr,socfpga-stmmac.yaml.
- Updated compatible in select properties and main properties.
- Fixed clocks so stmmaceth clock is required.
- Added binding for altr,gmii-to-sgmii.
- Update MAINTAINERS.
v3:
- Add missing supported phy-modes.
v2:
- Add compatible to required.
- Add descriptions for clocks.
- Add clock-names.
- Clean up items: in altr,sysmgr-syscon.
- Change "additionalProperties: true" to "unevaluatedProperties: false".
- Add properties needed for "unevaluatedProperties: false".
- Fix indentation in examples.
- Drop gmac0: label in examples.
- Exclude support for Arria10 that is not validating.
---
.../bindings/net/altr,gmii-to-sgmii-2.0.yaml | 49 ++++++
.../bindings/net/altr,socfpga-stmmac.yaml | 162 ++++++++++++++++++
.../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------
MAINTAINERS | 7 +-
4 files changed, 217 insertions(+), 58 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml
create mode 100644 Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
diff --git a/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml
new file mode 100644
index 000000000000..aafb6447b6c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2025 Altera Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii-2.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera GMII to SGMII Converter
+
+maintainers:
+ - Matthew Gerlach <matthew.gerlach@altera.com>
+
+description:
+ This binding describes the Altera GMII to SGMII converter.
+
+properties:
+ compatible:
+ const: altr,gmii-to-sgmii-2.0
+
+ reg:
+ items:
+ - description: Registers for the emac splitter IP
+ - description: Registers for the GMII to SGMII converter.
+ - description: Registers for TSE control.
+
+ reg-names:
+ items:
+ - const: hps_emac_interface_splitter_avalon_slave
+ - const: gmii_to_sgmii_adapter_avalon_slave
+ - const: eth_tse_control_port
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ phy@ff000240 {
+ compatible = "altr,gmii-to-sgmii-2.0";
+ reg = <0xff000240 0x00000008>,
+ <0xff000200 0x00000040>,
+ <0xff000250 0x00000008>;
+ reg-names = "hps_emac_interface_splitter_avalon_slave",
+ "gmii_to_sgmii_adapter_avalon_slave",
+ "eth_tse_control_port";
+ };
diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
new file mode 100644
index 000000000000..ccbbdb870755
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA SoC DWMAC controller
+
+maintainers:
+ - Matthew Gerlach <matthew.gerlach@altera.com>
+
+description:
+ This binding describes the Altera SOCFPGA SoC implementation of the
+ Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
+ of chips.
+ # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
+ # does not validate against net/snps,dwmac.yaml.
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - altr,socfpga-stmmac
+ - altr,socfpga-stmmac-a10-s10
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: altr,socfpga-stmmac
+ - const: snps,dwmac-3.70a
+ - const: snps,dwmac
+ - items:
+ - const: altr,socfpga-stmmac-a10-s10
+ - const: snps,dwmac-3.74a
+ - const: snps,dwmac
+
+ clocks:
+ minItems: 1
+ items:
+ - description: GMAC main clock
+ - description:
+ PTP reference clock. This clock is used for programming the
+ Timestamp Addend Register. If not passed then the system
+ clock will be used and this is fine on some platforms.
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: stmmaceth
+ - const: ptp_ref
+
+ iommus:
+ maxItems: 1
+
+ phy-mode:
+ enum:
+ - gmii
+ - mii
+ - rgmii
+ - rgmii-id
+ - rgmii-rxid
+ - rgmii-txid
+ - sgmii
+ - 1000base-x
+
+ rxc-skew-ps:
+ description: Skew control of RXC pad
+
+ rxd0-skew-ps:
+ description: Skew control of RX data 0 pad
+
+ rxd1-skew-ps:
+ description: Skew control of RX data 1 pad
+
+ rxd2-skew-ps:
+ description: Skew control of RX data 2 pad
+
+ rxd3-skew-ps:
+ description: Skew control of RX data 3 pad
+
+ rxdv-skew-ps:
+ description: Skew control of RX CTL pad
+
+ txc-skew-ps:
+ description: Skew control of TXC pad
+
+ txen-skew-ps:
+ description: Skew control of TXC pad
+
+ altr,emac-splitter:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should be the phandle to the emac splitter soft IP node if DWMAC
+ controller is connected an emac splitter.
+
+ altr,f2h_ptp_ref_clk:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to Precision Time Protocol reference clock. This clock is
+ common to gmac instances and defaults to osc1.
+
+ altr,gmii-to-sgmii-converter:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should be the phandle to the gmii to sgmii converter soft IP.
+
+ altr,sysmgr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Should be the phandle to the system manager node that encompass
+ the glue register, the register offset, and the register shift.
+ On Cyclone5/Arria5, the register shift represents the PHY mode
+ bits, while on the Arria10/Stratix10/Agilex platforms, the
+ register shift represents bit for each emac to enable/disable
+ signals from the FPGA fabric to the EMAC modules.
+ items:
+ - items:
+ - description: phandle to the system manager node
+ - description: offset of the control register
+ - description: shift within the control register
+
+patternProperties:
+ "^mdio[0-9]$":
+ type: object
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - altr,sysmgr-syscon
+
+allOf:
+ - $ref: snps,dwmac.yaml#
+
+unevaluatedProperties: false
+
+examples:
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ethernet@ff700000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
+ "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+ reg = <0xff700000 0x2000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
+ clocks = <&emac_0_clk>;
+ clock-names = "stmmaceth";
+ phy-mode = "sgmii";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
deleted file mode 100644
index 612a8e8abc88..000000000000
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-Altera SOCFPGA SoC DWMAC controller
-
-This is a variant of the dwmac/stmmac driver an inherits all descriptions
-present in Documentation/devicetree/bindings/net/stmmac.txt.
-
-The device node has additional properties:
-
-Required properties:
- - compatible : For Cyclone5/Arria5 SoCs it should contain
- "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
- "altr,socfpga-stmmac-a10-s10".
- Along with "snps,dwmac" and any applicable more detailed
- designware version numbers documented in stmmac.txt
- - altr,sysmgr-syscon : Should be the phandle to the system manager node that
- encompasses the glue register, the register offset, and the register shift.
- On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
- on the Arria10/Stratix10/Agilex platforms, the register shift represents
- bit for each emac to enable/disable signals from the FPGA fabric to the
- EMAC modules.
- - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
- for ptp ref clk. This affects all emacs as the clock is common.
-
-Optional properties:
-altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
- DWMAC controller is connected emac splitter.
-phy-mode: The phy mode the ethernet operates in
-altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
-
-This device node has additional phandle dependency, the sgmii converter:
-
-Required properties:
- - compatible : Should be altr,gmii-to-sgmii-2.0
- - reg-names : Should be "eth_tse_control_port"
-
-Example:
-
-gmii_to_sgmii_converter: phy@100000240 {
- compatible = "altr,gmii-to-sgmii-2.0";
- reg = <0x00000001 0x00000240 0x00000008>,
- <0x00000001 0x00000200 0x00000040>;
- reg-names = "eth_tse_control_port";
- clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
- clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
-};
-
-gmac0: ethernet@ff700000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x60 0>;
- reg = <0xff700000 0x2000>;
- interrupts = <0 115 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_0_clk>;
- clock-names = "stmmaceth";
- phy-mode = "sgmii";
- altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
-};
diff --git a/MAINTAINERS b/MAINTAINERS
index b8f217c7d92b..3e5aef9e1538 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3262,10 +3262,15 @@ M: Dinh Nguyen <dinguyen@kernel.org>
S: Maintained
F: drivers/clk/socfpga/
+ARM/SOCFPGA DWMAC GLUE LAYER BINDINGS
+M: Matthew Gerlach <matthew.gerlach@altera.com>
+S: Maintained
+F: Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml
+F: Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
+
ARM/SOCFPGA DWMAC GLUE LAYER
M: Maxime Chevallier <maxime.chevallier@bootlin.com>
S: Maintained
-F: Documentation/devicetree/bindings/net/socfpga-dwmac.txt
F: drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
ARM/SOCFPGA EDAC BINDINGS
--
2.35.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v5] dt-bindings: net: Convert socfpga-dwmac bindings to yaml
2025-06-12 22:16 [PATCH v5] dt-bindings: net: Convert socfpga-dwmac bindings to yaml Matthew Gerlach
@ 2025-06-13 6:14 ` Maxime Chevallier
2025-06-13 12:11 ` kernel test robot
1 sibling, 0 replies; 3+ messages in thread
From: Maxime Chevallier @ 2025-06-13 6:14 UTC (permalink / raw)
To: Matthew Gerlach
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, robh, krzk+dt,
conor+dt, mcoquelin.stm32, alexandre.torgue, richardcochran,
netdev, devicetree, linux-kernel, linux-stm32, linux-arm-kernel,
Mun Yew Tham
Hello Matthew,
On Thu, 12 Jun 2025 15:16:30 -0700
Matthew Gerlach <matthew.gerlach@altera.com> wrote:
> Convert the bindings for socfpga-dwmac to yaml. Since the original
> text contained descriptions for two separate nodes, two separate
> yaml files were created.
>
> Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Sorry I've been spending some time away from netdev@ lately... This
looks very good, again thanks !
Unless there's some more comments from the DT bindings maintainers, you
can add my :
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Maxime
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v5] dt-bindings: net: Convert socfpga-dwmac bindings to yaml
2025-06-12 22:16 [PATCH v5] dt-bindings: net: Convert socfpga-dwmac bindings to yaml Matthew Gerlach
2025-06-13 6:14 ` Maxime Chevallier
@ 2025-06-13 12:11 ` kernel test robot
1 sibling, 0 replies; 3+ messages in thread
From: kernel test robot @ 2025-06-13 12:11 UTC (permalink / raw)
To: Matthew Gerlach, andrew+netdev, davem, edumazet, kuba, pabeni,
robh, krzk+dt, conor+dt, maxime.chevallier, mcoquelin.stm32,
alexandre.torgue, richardcochran, netdev, devicetree,
linux-kernel, linux-stm32, linux-arm-kernel
Cc: oe-kbuild-all, Matthew Gerlach, Mun Yew Tham
Hi Matthew,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on net-next/main net/main linus/master v6.16-rc1 next-20250613]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Matthew-Gerlach/dt-bindings-net-Convert-socfpga-dwmac-bindings-to-yaml/20250613-062051
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20250612221630.45198-1-matthew.gerlach%40altera.com
patch subject: [PATCH v5] dt-bindings: net: Convert socfpga-dwmac bindings to yaml
reproduce: (https://download.01.org/0day-ci/archive/20250613/202506131908.dH1ks6AW-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202506131908.dH1ks6AW-lkp@intel.com/
All warnings (new ones prefixed by >>):
Warning: Documentation/translations/zh_CN/admin-guide/README.rst references a file that doesn't exist: Documentation/dev-tools/kgdb.rst
Warning: Documentation/translations/zh_CN/dev-tools/gdb-kernel-debugging.rst references a file that doesn't exist: Documentation/dev-tools/gdb-kernel-debugging.rst
Warning: Documentation/translations/zh_CN/how-to.rst references a file that doesn't exist: Documentation/xxx/xxx.rst
Warning: Documentation/translations/zh_TW/admin-guide/README.rst references a file that doesn't exist: Documentation/dev-tools/kgdb.rst
Warning: Documentation/translations/zh_TW/dev-tools/gdb-kernel-debugging.rst references a file that doesn't exist: Documentation/dev-tools/gdb-kernel-debugging.rst
>> Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml
Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/leds/ti,tps6131x.yaml
Warning: arch/riscv/kernel/kexec_image.c references a file that doesn't exist: Documentation/riscv/boot-image-header.rst
Warning: drivers/clocksource/timer-armada-370-xp.c references a file that doesn't exist: Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
Using alabaster theme
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-06-12 22:16 [PATCH v5] dt-bindings: net: Convert socfpga-dwmac bindings to yaml Matthew Gerlach
2025-06-13 6:14 ` Maxime Chevallier
2025-06-13 12:11 ` kernel test robot
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