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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:13 -0700 (PDT) From: Nick Chan Subject: [PATCH RESEND v7 00/21] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Date: Mon, 16 Jun 2025 09:31:49 +0800 Message-Id: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4111; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=IImZvUkpMAnwhvmBNPBZuUuP3+ZC7bdMT4Tj48zkB6M=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QWFDqwdlCT87E/lnHN0y3uxYwVNCrcfXdEv r8W31VQ5I6JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90FgAKCRABygi3psUI JHOcD/9aqE6YzKXZcdiBW5LIR1CLL8vrnqMP86Z4ipOHcMcJQdQT15eeRJduzxpeFzUHsqqlVko S9wtuUkyLZlSRNuwIzyh9bkSDMvgTIMCcmGqpNIgNbqZ9IN8AeYyxjfJUUqoZ6q9wn7e1j85aDS BRAYn0al8oDlTlWq+LPbEvMJtGdc+oYqt5scMf9V68svvEdjqsSqL/DpUGtH7obA6hYmx77etoa FFPkshJ8PGB+WAFWxQkSm02PU8YxFzv0TZtxJwH3t2J7i6arjJfAURZt26JL7rFNZXsTq1hCIlK bN5fFrzAMwFtrLAox+nZ4wUDBJLTl8bWvSN9ur9Ny3MPvlBxifUEtnsEslTP2OsGXzhVF22Xesr bFoA8m3ZdGrrFH+VNsLJxys1NNkiWHDzh3wj8c/JENOFtDdU08WLZr65UatfL10vzvCNyJHYSKJ oU80Bszn2ITw2U3knG/X2MTklcmDHK7/xkWRmiTnPJrNBQu6SJOAJkhvKtJ3cTWaiwnBE/qIvfh C+ECXbFaoNIwW+56dUdKRRGcFpFz0LWt1BhKa5QZ6Q8qxYSGZwr+oc/8TOpSNaCNWnYpIRpi8bY F3EhnhR6lLnxPffH2+YqunJwEFDPWlVgZlj/E2AaX6SWiS33WoDsKo7uL/zQDDFybZqbvEU/iRZ 9EkuYkCRyCg4khg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 This series adds support for the CPU PMU in the older Apple A7-A11, T2 SoCs. These PMUs may have a different event layout, less counters, or deliver their interrupts via IRQ instead of a FIQ. Since some of those older SoCs support 32-bit EL0, counting for 32-bit EL0 also need to be enabled by the driver where applicable. Patch 1 adds the DT bindings. Patch 2-7 prepares the driver to allow adding support for those older SoCs. Patch 8-12 adds support for the older SoCs. Patch 13-21 are the DT changes. Signed-off-by: Nick Chan --- Changes in v7: - Fix a W=1 compile warning in apple_pmu_get_event_idx() as appearently using GENMASK() in a function prototype causes a warning in GCC. - Link to v6: https://lore.kernel.org/r/20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com Changes in v6: - Rebased on top of v6.15-rc1 (Conflict with FEAT_PMUv3 support for KVM on Apple Hardware) - Add patch to skip initialization of PMUv3 remap in EL1 even though not strictly needed - Include DT patches - Link to v5: https://lore.kernel.org/r/20250228-apple-cpmu-v5-0-9e124cd28ed4@gmail.com Changes in v5: - Slightly change "drivers/perf: apple_m1: Add Apple A11 Support", to keep things in chronological order. - Link to v4: https://lore.kernel.org/r/20250214-apple-cpmu-v4-0-ffca0e45147e@gmail.com Changes in v4: - Support per-implementation event attr group - Fix Apple A7 event attr groups - Link to v3: https://lore.kernel.org/r/20250213-apple-cpmu-v3-0-be7f8aded81f@gmail.com Changes in v3: - Configure PMC8 and PMC9 for 32-bit EL0 - Remove redundant _common suffix from shared functions - Link to v2: https://lore.kernel.org/r/20250213-apple-cpmu-v2-0-87b361932e88@gmail.com Changes in v2: - Remove unused flags parameter from apple_pmu_init_common() - Link to v1: https://lore.kernel.org/r/20250212-apple-cpmu-v1-0-f8c7f2ac1743@gmail.com --- Nick Chan (21): dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles drivers/perf: apple_m1: Only init PMUv3 remap when EL2 is available drivers/perf: apple_m1: Support per-implementation event tables drivers/perf: apple_m1: Support a per-implementation number of counters drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 drivers/perf: apple_m1: Support per-implementation PMU startup drivers/perf: apple_m1: Support per-implementation event attr group drivers/perf: apple_m1: Add Apple A7 support drivers/perf: apple_m1: Add Apple A8/A8X support drivers/perf: apple_m1: Add A9/A9X support drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support drivers/perf: apple_m1: Add Apple A11 Support arm64: dts: apple: s5l8960x: Add CPU PMU nodes arm64: dts: apple: t7000: Add CPU PMU nodes arm64: dts: apple: t7001: Add CPU PMU nodes arm64: dts: apple: s800-0-3: Add CPU PMU nodes arm64: dts: apple: s8001: Add CPU PMU nodes arm64: dts: apple: t8010: Add CPU PMU nodes arm64: dts: apple: t8011: Add CPU PMU nodes arm64: dts: apple: t8012: Add CPU PMU nodes arm64: dts: apple: t8015: Add CPU PMU nodes Documentation/devicetree/bindings/arm/pmu.yaml | 6 + arch/arm64/boot/dts/apple/s5l8960x.dtsi | 8 + arch/arm64/boot/dts/apple/s800-0-3.dtsi | 8 + arch/arm64/boot/dts/apple/s8001.dtsi | 8 + arch/arm64/boot/dts/apple/t7000.dtsi | 8 + arch/arm64/boot/dts/apple/t7001.dtsi | 9 + arch/arm64/boot/dts/apple/t8010.dtsi | 8 + arch/arm64/boot/dts/apple/t8011.dtsi | 9 + arch/arm64/boot/dts/apple/t8012.dtsi | 8 + arch/arm64/boot/dts/apple/t8015.dtsi | 24 + arch/arm64/include/asm/apple_m1_pmu.h | 3 + drivers/perf/apple_m1_cpu_pmu.c | 807 +++++++++++++++++++++++-- 12 files changed, 871 insertions(+), 35 deletions(-) --- base-commit: 0af2f6be1b4281385b618cb86ad946eded089ac8 change-id: 20250211-apple-cpmu-5a5a3da39483 Best regards, -- Nick Chan