From: Christian Marangi <ansuelsmth@gmail.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Felix Fietkau <nbd@nbd.name>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Christian Marangi <ansuelsmth@gmail.com>
Subject: [PATCH v2 03/10] clk: en7523: convert to full clk_hw implementation
Date: Tue, 17 Jun 2025 15:04:46 +0200 [thread overview]
Message-ID: <20250617130455.32682-4-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com>
In preparation for support of .set_rate, convert the clock register
logic from fixed clock implementation to full clk_hw implementation with
dedicated OPs.
This is just a rework and no behaviour change is expected.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 83 ++++++++++++++++++++++++++++------------
1 file changed, 59 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index b040f0f0d727..10fb0dcdc88b 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -69,6 +69,12 @@ struct en_clk_gate {
struct clk_hw hw;
};
+struct en_clk {
+ struct regmap *map;
+ const struct en_clk_desc *desc;
+ struct clk_hw hw;
+};
+
struct en_rst_data {
const u16 *bank_ofs;
const u16 *idx_map;
@@ -471,44 +477,73 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
return &cg->hw;
}
+static unsigned long en75xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct en_clk *c = container_of(hw, struct en_clk, hw);
+ const struct en_clk_desc *desc = c->desc;
+ struct regmap *map = c->map;
+ u32 val, reg;
+ u32 rate;
+ int err;
+
+ err = regmap_read(map, desc->base_reg, &val);
+ if (err) {
+ pr_err("Failed reading fixed clk rate %s: %d\n",
+ desc->name, err);
+ return err;
+ }
+ rate = en7523_get_base_rate(desc, val);
+
+ reg = desc->div_reg ? desc->div_reg : desc->base_reg;
+ err = regmap_read(map, reg, &val);
+ if (err) {
+ pr_err("Failed reading fixed clk div %s: %d\n",
+ desc->name, err);
+ return err;
+ }
+
+ return rate / en7523_get_div(desc, val);
+}
+
+static const struct clk_ops en75xx_clk_ops = {
+ .recalc_rate = en75xx_recalc_rate,
+};
+
static int en75xx_register_clocks(struct device *dev,
const struct en_clk_soc_data *soc_data,
struct clk_hw_onecell_data *clk_data,
struct regmap *map, struct regmap *clk_map)
{
struct clk_hw *hw;
- u32 rate;
int i;
for (i = 0; i < soc_data->num_clocks - 1; i++) {
const struct en_clk_desc *desc = &soc_data->base_clks[i];
- u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;
+ struct clk_init_data init = {
+ .ops = &en75xx_clk_ops,
+ };
+ struct en_clk *en_clk;
int err;
- err = regmap_read(map, desc->base_reg, &val);
- if (err) {
- pr_err("Failed reading fixed clk rate %s: %d\n",
- desc->name, err);
- return err;
- }
- rate = en7523_get_base_rate(desc, val);
+ en_clk = devm_kzalloc(dev, sizeof(*en_clk), GFP_KERNEL);
+ if (!en_clk)
+ return -ENOMEM;
- err = regmap_read(map, reg, &val);
+ init.name = desc->name;
+
+ en_clk->map = map;
+ en_clk->desc = desc;
+ en_clk->hw.init = &init;
+
+ err = devm_clk_hw_register(dev, &en_clk->hw);
if (err) {
- pr_err("Failed reading fixed clk div %s: %d\n",
+ pr_err("Failed to register clk %s: %d\n",
desc->name, err);
return err;
}
- rate /= en7523_get_div(desc, val);
-
- hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
- if (IS_ERR(hw)) {
- pr_err("Failed to register clk %s: %ld\n",
- desc->name, PTR_ERR(hw));
- return PTR_ERR(hw);
- }
- clk_data->hws[desc->id] = hw;
+ clk_data->hws[desc->id] = &en_clk->hw;
}
hw = en7523_register_pcie_clk(dev, clk_map);
@@ -672,7 +707,7 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
{
struct regmap *map, *clk_map;
void __iomem *base;
- int ret;
+ int err;
map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
if (IS_ERR(map))
@@ -686,9 +721,9 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
if (IS_ERR(clk_map))
return PTR_ERR(clk_map);
- ret = en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_map);
- if (ret)
- return ret;
+ err = en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_map);
+ if (err)
+ return err;
regmap_clear_bits(clk_map, REG_NP_SCU_SSTR,
REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
--
2.48.1
next prev parent reply other threads:[~2025-06-17 13:05 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 13:04 [PATCH v2 00/10] clk: add support for Airoha AN7583 clock Christian Marangi
2025-06-17 13:04 ` [PATCH v2 01/10] clk: en7523: convert driver to regmap API Christian Marangi
2025-06-17 13:04 ` [PATCH v2 02/10] clk: en7523: generalize register clocks function Christian Marangi
2025-06-17 13:04 ` Christian Marangi [this message]
2025-06-17 13:04 ` [PATCH v2 04/10] clk: en7523: add support for .set_rate Christian Marangi
2025-06-17 13:04 ` [PATCH v2 05/10] clk: en7523: permit to reference Chip SCU from phandle Christian Marangi
2025-06-17 13:04 ` [PATCH v2 06/10] dt-bindings: clock: airoha: Document new property airoha,chip-scu Christian Marangi
2025-06-27 7:59 ` Krzysztof Kozlowski
2025-06-27 8:20 ` Christian Marangi
2025-07-16 14:29 ` Krzysztof Kozlowski
2025-07-21 19:06 ` Christian Marangi
2025-06-17 13:04 ` [PATCH v2 07/10] clk: en7523: reword and clean clk_probe variables Christian Marangi
2025-06-17 13:04 ` [PATCH v2 08/10] clk: en7523: add support for probing SCU child Christian Marangi
2025-06-17 13:04 ` [PATCH v2 09/10] dt-bindings: clock: airoha: Document support for AN7583 clock Christian Marangi
2025-06-27 8:00 ` Krzysztof Kozlowski
2025-06-17 13:04 ` [PATCH v2 10/10] clk: en7523: add support for Airoha " Christian Marangi
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