* [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node
@ 2025-06-18 1:58 Inochi Amaoto
2025-06-18 1:58 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: add MSI device support for SG2044 Inochi Amaoto
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Inochi Amaoto @ 2025-06-18 1:58 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Longbin Li
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan
As the PCIe driver is merged, add device node of PCIe device and MSI
device for SG2044.
Inochi Amaoto (2):
riscv: dts: sophgo: sg2044: add MSI device support for SG2044
riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
.../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 34 ++++
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 186 ++++++++++++++++++
2 files changed, 220 insertions(+)
--
2.49.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] riscv: dts: sophgo: sg2044: add MSI device support for SG2044
2025-06-18 1:58 [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node Inochi Amaoto
@ 2025-06-18 1:58 ` Inochi Amaoto
2025-06-19 7:13 ` Chen Wang
2025-06-18 1:58 ` [PATCH 2/2] riscv: dts: sophgo: sg2044: add PCIe " Inochi Amaoto
2025-07-07 0:31 ` [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node Inochi Amaoto
2 siblings, 1 reply; 5+ messages in thread
From: Inochi Amaoto @ 2025-06-18 1:58 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Longbin Li
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan
Add MSI device tree node for SG2044.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 11 +++++++++++
2 files changed, 15 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
index b50c3a872d8b..c97bd62e5f06 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
@@ -63,6 +63,10 @@ mcu: syscon@17 {
};
};
+&msi {
+ status = "okay";
+};
+
&pwm {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index f88cabe75790..aae4539dea98 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -32,6 +32,17 @@ soc {
#size-cells = <2>;
ranges;
+ msi: msi-controller@6d50000000 {
+ compatible = "sophgo,sg2044-msi";
+ reg = <0x6d 0x50000000 0x0 0x800>,
+ <0x0 0x7ee00000 0x0 0x40>;
+ reg-names = "clr", "doorbell";
+ #msi-cells = <0>;
+ msi-controller;
+ msi-ranges = <&intc 352 IRQ_TYPE_LEVEL_HIGH 512>;
+ status = "disabled";
+ };
+
spifmc0: spi@7001000000 {
compatible = "sophgo,sg2044-spifmc-nor";
reg = <0x70 0x01000000 0x0 0x4000000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
2025-06-18 1:58 [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node Inochi Amaoto
2025-06-18 1:58 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: add MSI device support for SG2044 Inochi Amaoto
@ 2025-06-18 1:58 ` Inochi Amaoto
2025-07-07 0:31 ` [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node Inochi Amaoto
2 siblings, 0 replies; 5+ messages in thread
From: Inochi Amaoto @ 2025-06-18 1:58 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Chen Wang, Inochi Amaoto, Longbin Li
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan
Add PCIe device node for SG2044 and configuration for Sophgo SRD3-10.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
.../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 30 +++
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 175 ++++++++++++++++++
2 files changed, 205 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
index c97bd62e5f06..1ca5fb707061 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
@@ -67,6 +67,36 @@ &msi {
status = "okay";
};
+&pcie0 {
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <1>;
+ status = "okay";
+};
+
+&pcie1 {
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <0>;
+ status = "okay";
+};
+
+&pcie2 {
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <3>;
+ status = "okay";
+};
+
+&pcie3 {
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <2>;
+ status = "okay";
+};
+
+&pcie4 {
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <4>;
+ status = "okay";
+};
+
&pwm {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index aae4539dea98..6ec955744b0c 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -32,6 +32,181 @@ soc {
#size-cells = <2>;
ranges;
+ pcie0: pcie@6c00000000 {
+ compatible = "sophgo,sg2044-pcie";
+ reg = <0x6c 0x00000000 0x0 0x00001000>,
+ <0x6c 0x00300000 0x0 0x00004000>,
+ <0x48 0x00000000 0x0 0x00001000>,
+ <0x6c 0x000c0000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "app";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ clocks = <&clk CLK_GATE_PCIE_1G>;
+ clock-names = "core";
+ device_type = "pci";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ msi-parent = <&msi>;
+ ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>,
+ <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>,
+ <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>,
+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
+ status = "disabled";
+
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
+ };
+
+ pcie1: pcie@6c00400000 {
+ compatible = "sophgo,sg2044-pcie";
+ reg = <0x6c 0x00400000 0x0 0x00001000>,
+ <0x6c 0x00700000 0x0 0x00004000>,
+ <0x40 0x00000000 0x0 0x00001000>,
+ <0x6c 0x00780000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "app";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ clocks = <&clk CLK_GATE_PCIE_1G>;
+ clock-names = "core";
+ device_type = "pci";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ msi-parent = <&msi>;
+ ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
+ <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
+ <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>,
+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
+ status = "disabled";
+
+ pcie_intc1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
+ };
+
+ pcie2: pcie@6c04000000 {
+ compatible = "sophgo,sg2044-pcie";
+ reg = <0x6c 0x04000000 0x0 0x00001000>,
+ <0x6c 0x04300000 0x0 0x00004000>,
+ <0x58 0x00000000 0x0 0x00001000>,
+ <0x6c 0x040c0000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "app";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ clocks = <&clk CLK_GATE_PCIE_1G>;
+ clock-names = "core";
+ device_type = "pci";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+ <0 0 0 2 &pcie_intc2 1>,
+ <0 0 0 3 &pcie_intc2 2>,
+ <0 0 0 4 &pcie_intc2 3>;
+ msi-parent = <&msi>;
+ ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>,
+ <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>,
+ <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>,
+ <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
+ status = "disabled";
+
+ pcie_intc2: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
+ };
+
+ pcie3: pcie@6c04400000 {
+ compatible = "sophgo,sg2044-pcie";
+ reg = <0x6c 0x04400000 0x0 0x00001000>,
+ <0x6c 0x04700000 0x0 0x00004000>,
+ <0x50 0x00000000 0x0 0x00001000>,
+ <0x6c 0x04780000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "app";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ clocks = <&clk CLK_GATE_PCIE_1G>;
+ clock-names = "core";
+ device_type = "pci";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+ <0 0 0 2 &pcie_intc3 1>,
+ <0 0 0 3 &pcie_intc3 2>,
+ <0 0 0 4 &pcie_intc3 3>;
+ msi-parent = <&msi>;
+ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>,
+ <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>,
+ <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>,
+ <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
+ status = "disabled";
+
+ pcie_intc3: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
+ };
+
+ pcie4: pcie@6c08400000 {
+ compatible = "sophgo,sg2044-pcie";
+ reg = <0x6c 0x08400000 0x0 0x00001000>,
+ <0x6c 0x08700000 0x0 0x00004000>,
+ <0x60 0x00000000 0x0 0x00001000>,
+ <0x6c 0x08780000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "app";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ clocks = <&clk CLK_GATE_PCIE_1G>;
+ clock-names = "core";
+ device_type = "pci";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc4 0>,
+ <0 0 0 2 &pcie_intc4 1>,
+ <0 0 0 3 &pcie_intc4 2>,
+ <0 0 0 4 &pcie_intc4 3>;
+ msi-parent = <&msi>;
+ ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00200000>,
+ <0x42000000 0x0 0x40000000 0x0 0x40000000 0x0 0x04000000>,
+ <0x02000000 0x0 0x44000000 0x0 0x44000000 0x0 0x04000000>,
+ <0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
+ status = "disabled";
+
+ pcie_intc4: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
+ };
+
msi: msi-controller@6d50000000 {
compatible = "sophgo,sg2044-msi";
reg = <0x6d 0x50000000 0x0 0x800>,
--
2.49.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: sg2044: add MSI device support for SG2044
2025-06-18 1:58 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: add MSI device support for SG2044 Inochi Amaoto
@ 2025-06-19 7:13 ` Chen Wang
0 siblings, 0 replies; 5+ messages in thread
From: Chen Wang @ 2025-06-19 7:13 UTC (permalink / raw)
To: Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Longbin Li
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan
On 2025/6/18 9:58, Inochi Amaoto wrote:
> Add MSI device tree node for SG2044.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++
> arch/riscv/boot/dts/sophgo/sg2044.dtsi | 11 +++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
> index b50c3a872d8b..c97bd62e5f06 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
> +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
> @@ -63,6 +63,10 @@ mcu: syscon@17 {
> };
> };
>
> +&msi {
> + status = "okay";
> +};
> +
> &pwm {
> status = "okay";
> };
> diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
> index f88cabe75790..aae4539dea98 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
> @@ -32,6 +32,17 @@ soc {
> #size-cells = <2>;
> ranges;
>
> + msi: msi-controller@6d50000000 {
> + compatible = "sophgo,sg2044-msi";
> + reg = <0x6d 0x50000000 0x0 0x800>,
> + <0x0 0x7ee00000 0x0 0x40>;
> + reg-names = "clr", "doorbell";
> + #msi-cells = <0>;
> + msi-controller;
> + msi-ranges = <&intc 352 IRQ_TYPE_LEVEL_HIGH 512>;
> + status = "disabled";
> + };
> +
> spifmc0: spi@7001000000 {
> compatible = "sophgo,sg2044-spifmc-nor";
> reg = <0x70 0x01000000 0x0 0x4000000>;
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node
2025-06-18 1:58 [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node Inochi Amaoto
2025-06-18 1:58 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: add MSI device support for SG2044 Inochi Amaoto
2025-06-18 1:58 ` [PATCH 2/2] riscv: dts: sophgo: sg2044: add PCIe " Inochi Amaoto
@ 2025-07-07 0:31 ` Inochi Amaoto
2 siblings, 0 replies; 5+ messages in thread
From: Inochi Amaoto @ 2025-07-07 0:31 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Longbin Li,
Inochi Amaoto
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan
On Wed, 18 Jun 2025 09:58:47 +0800, Inochi Amaoto wrote:
> As the PCIe driver is merged, add device node of PCIe device and MSI
> device for SG2044.
>
> Inochi Amaoto (2):
> riscv: dts: sophgo: sg2044: add MSI device support for SG2044
> riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
>
> [...]
Applied to for-next, thanks!
[1/2] riscv: dts: sophgo: sg2044: add MSI device support for SG2044
https://github.com/sophgo/linux/commit/29ce381d6bc61b23024c6ee42a5745d4becb28c1
[2/2] riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
https://github.com/sophgo/linux/commit/55fd09df36d7c6ae59d82a7df5072827f65a0eb4
Thanks,
Inochi
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-07-07 0:32 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-18 1:58 [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node Inochi Amaoto
2025-06-18 1:58 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: add MSI device support for SG2044 Inochi Amaoto
2025-06-19 7:13 ` Chen Wang
2025-06-18 1:58 ` [PATCH 2/2] riscv: dts: sophgo: sg2044: add PCIe " Inochi Amaoto
2025-07-07 0:31 ` [PATCH 0/2] riscv: dts: sophgo: sg2044: add PCIe device node Inochi Amaoto
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