From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: tsbogend@alpha.franken.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, sander@svanheule.net,
markus.stockhausen@gmx.de
Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: [PATCH 1/4] mips: dts: cameo-rtl9302c: Add switch block
Date: Thu, 19 Jun 2025 13:07:51 +1200 [thread overview]
Message-ID: <20250619010754.3760612-2-chris.packham@alliedtelesis.co.nz> (raw)
In-Reply-To: <20250619010754.3760612-1-chris.packham@alliedtelesis.co.nz>
Add the switch port and phys to the cameo-rtl9302c-2x-rtl8224-2xge
board.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Notes:
This was originally part of the series adding the MDIO driver[1] however
the mips specific part wasn't picked up for net-next so I've rolled it
into this series of changes for linux-mips.
This is needed to comply with the updated bindings. It could
possibly be split to add the ports then the PHYs. Technically the
ports are the required property that dtbs_check will complain about
but it didn't seem worth separating out the PHYs.
[1] - https://lore.kernel.org/all/20250204030249.1965444-7-chris.packham@alliedtelesis.co.nz/
.../cameo-rtl9302c-2x-rtl8224-2xge.dts | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
index 6789bf374044..6f6a05d4088e 100644
--- a/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
+++ b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
@@ -71,3 +71,99 @@ partition@1180000 {
};
};
};
+
+&mdio0 {
+ /* External RTL8224 */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&mdio1 {
+ /* External RTL8224 */
+ phy4: ethernet-phy@0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ phy5: ethernet-phy@1 {
+ reg = <1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ phy6: ethernet-phy@2 {
+ reg = <2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ phy7: ethernet-phy@3 {
+ reg = <3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&switch0 {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ phy-handle = <&phy0>;
+ phy-mode = "usxgmii";
+ };
+ port@1 {
+ reg = <1>;
+ phy-handle = <&phy1>;
+ phy-mode = "usxgmii";
+ };
+ port@2 {
+ reg = <2>;
+ phy-handle = <&phy2>;
+ phy-mode = "usxgmii";
+ };
+ port@3 {
+ reg = <3>;
+ phy-handle = <&phy3>;
+ phy-mode = "usxgmii";
+ };
+ port@16 {
+ reg = <16>;
+ phy-handle = <&phy4>;
+ phy-mode = "usxgmii";
+ };
+ port@17 {
+ reg = <17>;
+ phy-handle = <&phy5>;
+ phy-mode = "usxgmii";
+ };
+ port@18 {
+ reg = <18>;
+ phy-handle = <&phy6>;
+ phy-mode = "usxgmii";
+ };
+ port@19 {
+ reg = <19>;
+ phy-handle = <&phy7>;
+ phy-mode = "usxgmii";
+ };
+ port@24{
+ reg = <24>;
+ phy-mode = "10gbase-r";
+ };
+ port@25{
+ reg = <25>;
+ phy-mode = "10gbase-r";
+ };
+ };
+};
--
2.49.0
next prev parent reply other threads:[~2025-06-19 1:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 1:07 [PATCH 0/4] mips: dts: Updates for RTL9300 Chris Packham
2025-06-19 1:07 ` Chris Packham [this message]
2025-06-19 1:07 ` [PATCH 2/4] mips: dts: realtek: Add switch interrupts Chris Packham
2025-06-19 1:07 ` [PATCH 3/4] mips: dts: realtek: Add watchdog Chris Packham
2025-06-19 1:07 ` [PATCH 4/4] mips: dts: realtek: Add gpio block Chris Packham
2025-07-02 12:02 ` [PATCH 0/4] mips: dts: Updates for RTL9300 Thomas Bogendoerfer
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