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([2409:4080:e3d:e62b:ab13:6038:4535:e5a2]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d8695000sm13147425ad.186.2025.06.20.02.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jun 2025 02:14:42 -0700 (PDT) From: Shankari Anand To: devicetree@vger.kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthew.gerlach@altera.com, Shankari Anand Subject: [PATCH v5] dt-bindings: memory-controllers: Convert Altera SDRAM EDAC .txt to YAML Date: Fri, 20 Jun 2025 14:44:29 +0530 Message-Id: <20250620091429.388981-1-shankari.ak0208@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert the Altera SOCFPGA SDRAM EDAC devicetree binding from the .txt format to a YAML schema. Added a 'reg' property as dt_binding_check flagged its absence. The controller is memory-mapped; address is confirmed from Intel's manual. Also added two strings: altr,sdram-edac-a10 and altr,sdram-edac-s10, compatible with altr,sdram-edac but use two interrupts; Schema enforces interrupt count per variant. Signed-off-by: Shankari Anand --- v4 -> v5: Updated commit message, fixed placement of reg, added allOf condition per variant, fixed example section, dropped description as specified Reference for reg address - https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#topic/sfo1429889205804.html , https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html#bal1505408006582.html --- .../arm/altera/socfpga-sdram-edac.txt | 15 --- .../memory-controllers/altr,sdram-edac.yaml | 104 ++++++++++++++++++ 2 files changed, 104 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/altr,sdram-edac.yaml diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt deleted file mode 100644 index f5ad0ff69fae..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt +++ /dev/null @@ -1,15 +0,0 @@ -Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] -The EDAC accesses a range of registers in the SDRAM controller. - -Required properties: -- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10" -- altr,sdr-syscon : phandle of the sdr module -- interrupts : Should contain the SDRAM ECC IRQ in the - appropriate format for the IRQ controller. - -Example: - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/altr,sdram-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/altr,sdram-edac.yaml new file mode 100644 index 000000000000..652289c2c2f4 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/altr,sdram-edac.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/altr,sdram-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SoCFPGA SDRAM EDAC Controller + +maintainers: + - Matthew Gerlach + +description: | + EDAC-compatible controller for SDRAM error detection and correction on + Altera (Intel) SoCFPGA platforms. + +properties: + compatible: + enum: + - altr,sdram-edac + - altr,sdram-edac-a10 + - altr,sdram-edac-s10 + + reg: + maxItems: 1 + + altr,sdr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the SDRAM system controller (SDR) syscon node. + + interrupts: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - altr,sdr-syscon + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + enum: + - altr,sdram-edac-a10 + - altr,sdram-edac-s10 + then: + properties: + interrupts: + minItems: 2 + +additionalProperties: false + +examples: + - | + #include + #include + + / { + model = "Example SoC with SDRAM EDAC"; + compatible = "arm-soc"; + + #address-cells = <1>; + #size-cells = <1>; + + intc: interrupt-controller@0 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x1000>, <0x1000 0x1000>; // Dummy + }; + + sdr: syscon@f8000000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xf8000000 0x1000>; // Dummy + }; + + memory-controller@f8004000 { + compatible = "altr,sdram-edac-a10"; + reg = <0xf8004000 0x1000>; + altr,sdr-syscon = <&sdr>; + interrupt-parent = <&intc>; + interrupts = , + ; + }; + + memory-controller@f8011000 { + compatible = "altr,sdram-edac-s10"; + reg = <0xf8011000 0x1000>; + altr,sdr-syscon = <&sdr>; + interrupt-parent = <&intc>; + interrupts = , + ; + }; + + memory-controller@ffc25000 { + compatible = "altr,sdram-edac"; + reg = <0xffc25000 0x1000>; + altr,sdr-syscon = <&sdr>; + interrupt-parent = <&intc>; + interrupts = ; + }; + }; -- 2.34.1