From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8A6E42A96 for ; Sat, 21 Jun 2025 03:44:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750477453; cv=none; b=rjxAJH8UCReKa9VbkzO1queT5N+V6Fgy4PYcGrhBqCPQPavfeknz3T4BiP/FJMh+DWQg9aeZTGoh8nmM/2cXKLyG9AtqMKZMh/Xj2R+ZsLcw5A9ZqDfKXswaJWtiC4L48Bo/+yeJloh2jKvV+tuWaL0c4ymDugs97NC7njepHpw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750477453; c=relaxed/simple; bh=5F1fbcphphxLuGVY7fTghBHaNk2e0TiajscUaQKz9rM=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=qbNRZsWMueJlpXXzHAeM3iBWDMP0PBRTNUSu0HAytiaci9Fwq1wgjEpdID97D2qtCvbjV88bHl9Sdf2pVoXh9M/6wmiiZXZFH+hvV8f84EAJyG/pGRL4r0KFycaRxBxZRFv416xvrxv8RJ3Sc8dezCTRwXHhtPNDNAn07SELXhw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QE/vqawR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QE/vqawR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BCE3BC4CEE7; Sat, 21 Jun 2025 03:44:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750477453; bh=5F1fbcphphxLuGVY7fTghBHaNk2e0TiajscUaQKz9rM=; h=From:To:Cc:Subject:Date:From; b=QE/vqawRoQPJG9YfanMs9cE1LgWejTlnHBSGPi1i0piBA2zANFxtMZhkOC/INQ9BK HFusSN0NfkjnPlIuujNnusEBPHQA0gR4FE736p//C885mbNj/+7ksAx/93jVtTLdTL PJkg5AEtCyeGqcjLOM7HxGlqoRMmsDCYyqtzkBOz2KKw8mdwtFsfSTlwBm8LbQXRLQ d04ulYEolAerl8zlsR0sJlbEYRvbQWqDSozFRxBnDX37PrEoWivbPCPyzJsteuNa96 /A5fbQA0xTDyIeakDceOfli6P490vRGNM2H9JPIr7yOtw3hh/4fVczQpXnlyz84jZ7 y1UIqRHe4Pmdg== From: Dinh Nguyen To: robh+dt@kernel.org, krzysztof.kozlowskii+dt@linaro.org, conor+dt@kernel.org Cc: dinguyen@kernel.org, devicetree@vger.kernel.org Subject: [PATCH] dt-bindings: net: convert socfpga-dwmac.txt to DT schema Date: Fri, 20 Jun 2025 22:44:01 -0500 Message-ID: <20250621034401.586780-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.42.0.411.g813d9a9188 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert the socfpga-dwmac.txt to yaml. Signed-off-by: Dinh Nguyen --- .../bindings/net/altr,dwmac-socfpga.yaml | 152 ++++++++++++++++++ .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------- 2 files changed, 152 insertions(+), 57 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt diff --git a/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml b/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml new file mode 100644 index 000000000000..fc088bd55178 --- /dev/null +++ b/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/altr,dwmac-socfpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel/Altera SoCFPGA DWMAC controller + +maintainers: + - Dinh Nguyen + +properties: + compatible: + additionalItems: true + maxItems: 3 + items: + - enum: + - altr,socfpga-stmmac + - altr,socfpga-stmmac-a10-s10 + contains: + enum: + - snps,dwmac-3.74a + - snps,dwmac-3.70a + - snps,dwmac + + reg: + items: + - description: Base DWMAC registers + + iommus: + minItems: 1 + maxItems: 2 + + clocks: + minItems: 1 + items: + - description: MAC host clock + - description: MAC timer clock + + clock-names: + minItems: 1 + maxItems: 2 + contains: + enum: + - stmmaceth + - ptp_ref + + resets: + minItems: 1 + items: + - description: GMAC stmmaceth reset + - description: AHB reset + + reset-names: + oneOf: + - items: + - enum: [stmmaceth, ahb] + - items: + - const: stmmaceth + - const: ahb + + interrupts: + items: + - description: DWAC interrupt + + interrupt-names: + items: + - const: macirq + + mac-address: true + + phy-mode: + maxItems: 1 + items: + enum: + - rgmii + - gmii + - mii + + tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: DWMAC Tx fifo depth(Stratix10, Agilex) + + rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: DWMAC Rx fifo depth(Stratix10, Agilex) + + snps,multicast-filter-bins: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of multicast filter hash bins supported by this device + instance + + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + description: + Should be the phandle to the system manager node that + encompasses the glue register, the register offset, and the register shift. + On Cyclone5/Arria5, the register shift represents the PHY mode bits, while + on the Arria10/Stratix10/Agilex platforms, the register shift represents + bit for each emac to enable/disable signals from the FPGA fabric to the + EMAC modules. + + altr,emac-splitter: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Should be the phandle to the emac splitter soft IP node if DWMAC + controller is connected emac splitter. + + altr,sgmii-to-sgmii-converter: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the TSE SGMII converter. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phy-mode + +allOf: + - $ref: snps,dwmac.yaml# + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac_0_clk>; + clock-names = "stmmaceth"; + phy-mode = "rgmii"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt deleted file mode 100644 index 612a8e8abc88..000000000000 --- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt +++ /dev/null @@ -1,57 +0,0 @@ -Altera SOCFPGA SoC DWMAC controller - -This is a variant of the dwmac/stmmac driver an inherits all descriptions -present in Documentation/devicetree/bindings/net/stmmac.txt. - -The device node has additional properties: - -Required properties: - - compatible : For Cyclone5/Arria5 SoCs it should contain - "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs - "altr,socfpga-stmmac-a10-s10". - Along with "snps,dwmac" and any applicable more detailed - designware version numbers documented in stmmac.txt - - altr,sysmgr-syscon : Should be the phandle to the system manager node that - encompasses the glue register, the register offset, and the register shift. - On Cyclone5/Arria5, the register shift represents the PHY mode bits, while - on the Arria10/Stratix10/Agilex platforms, the register shift represents - bit for each emac to enable/disable signals from the FPGA fabric to the - EMAC modules. - - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock - for ptp ref clk. This affects all emacs as the clock is common. - -Optional properties: -altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if - DWMAC controller is connected emac splitter. -phy-mode: The phy mode the ethernet operates in -altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter - -This device node has additional phandle dependency, the sgmii converter: - -Required properties: - - compatible : Should be altr,gmii-to-sgmii-2.0 - - reg-names : Should be "eth_tse_control_port" - -Example: - -gmii_to_sgmii_converter: phy@100000240 { - compatible = "altr,gmii-to-sgmii-2.0"; - reg = <0x00000001 0x00000240 0x00000008>, - <0x00000001 0x00000200 0x00000040>; - reg-names = "eth_tse_control_port"; - clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>; - clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; -}; - -gmac0: ethernet@ff700000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 0>; - reg = <0xff700000 0x2000>; - interrupts = <0 115 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac_0_clk>; - clock-names = "stmmaceth"; - phy-mode = "sgmii"; - altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>; -}; -- 2.42.0.411.g813d9a9188