From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AC5123A994; Mon, 23 Jun 2025 09:30:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750671007; cv=none; b=g3doipCGDFJZPLLgGm4VTNH3JneGEuY+2eNHCXzRJ/BNVQbtdaZf3M3bvYD3thIQHmWhKVR+NYDYujKr4fYMuCvy+A9bCKzoWigMPYiBQ/Y9eo41JeW7l9DEN9GkSpVtUYlu7Za/uv4tVD2j8zkHhD/YrYr4fdP7YLFh/TDWmR8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750671007; c=relaxed/simple; bh=zHL0/JrntZk6f9z9OaKUCRl5Ve/+xb8bifr4gesVLAc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=NWiii8b/5C/q9OsPyglqdRaeBxPhE0o5AjVTVKbbY9P93U5lzVicUgK5UGivFPlPKYiRkefe9hWFxSYdEUNdQpxnBHCRUC0kbY6IAejLs4sHAj3GZm7DPTG/tQ+av1Ff//Qbuu83yDMJhBVLDLaMbWg/YuglsCKF9NRW8UisrOQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=jQPh+kQx; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="jQPh+kQx" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55N8xDEl024011; Mon, 23 Jun 2025 11:29:35 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= c84xGmzk0WDtYO8pxiXJLl1Oz2OVFtl3JU/pJXFAfdc=; b=jQPh+kQxUnHvfPcA KzZiHgX4bkjM2hZCal54YdDqFf43W50G03KtAZI5j13pwnlAvpLfG8wzk2v7YTMo qTvTCQ5+1jFUFZg+QoCHMDYIyHSuPdhBkn2SHRxhzrMeeE4REROEEJkzhI+wE39a XwpMgzIVRj61Hv+L3c8zG+HB+iER+oOhmnxGWvTOiHebTwmZ4YUKHYPPd4L40hDf RJc9YiqrhlzMyLlKFHMJutM4nOlFB8UnBiB992VlnDOzKEHkzSjUFCYnp6+uFMTo Ll07eqSBHeoGY70vfO2yYYF792cjQA2NntkXBmZyrO/jzYepKm+mP6zl1lesfclz N/clqA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 47e7pp4932-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 23 Jun 2025 11:29:35 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 261FC4004A; Mon, 23 Jun 2025 11:28:30 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9A9B15C2DFF; Mon, 23 Jun 2025 11:27:23 +0200 (CEST) Received: from localhost (10.252.18.29) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 23 Jun 2025 11:27:23 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 23 Jun 2025 11:27:08 +0200 Subject: [PATCH 03/13] clk: stm32mp25: add firewall grant_access ops Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-ID: <20250623-ddrperfm-upstream-v1-3-7dffff168090@foss.st.com> References: <20250623-ddrperfm-upstream-v1-0-7dffff168090@foss.st.com> In-Reply-To: <20250623-ddrperfm-upstream-v1-0-7dffff168090@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-c25d1 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-23_03,2025-06-23_02,2025-03-28_01 On STM32MP25, the RCC peripheral manages the secure level of resources that are used by other devices such as clocks. Declare this peripheral as a firewall controller. Signed-off-by: Clément Le Goffic --- drivers/clk/stm32/clk-stm32mp25.c | 40 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c index 52f0e8a12926..af4bc06d703a 100644 --- a/drivers/clk/stm32/clk-stm32mp25.c +++ b/drivers/clk/stm32/clk-stm32mp25.c @@ -4,8 +4,10 @@ * Author: Gabriel Fernandez for STMicroelectronics. */ +#include #include #include +#include #include #include @@ -1602,6 +1604,11 @@ static int stm32_rcc_get_access(void __iomem *base, u32 index) return 0; } +static int stm32mp25_rcc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + return stm32_rcc_get_access(ctrl->mmio, firewall_id); +} + static int stm32mp25_check_security(struct device_node *np, void __iomem *base, const struct clock_config *cfg) { @@ -1970,6 +1977,7 @@ MODULE_DEVICE_TABLE(of, stm32mp25_match_data); static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev) { + struct stm32_firewall_controller *rcc_controller; struct device *dev = &pdev->dev; void __iomem *base; int ret; @@ -1982,7 +1990,36 @@ static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev) if (ret) return ret; - return stm32_rcc_init(dev, stm32mp25_match_data, base); + ret = stm32_rcc_init(dev, stm32mp25_match_data, base); + if (ret) + return ret; + + rcc_controller = devm_kzalloc(&pdev->dev, sizeof(*rcc_controller), GFP_KERNEL); + if (!rcc_controller) + return -ENOMEM; + + rcc_controller->dev = dev; + rcc_controller->mmio = base; + rcc_controller->name = dev_driver_string(dev); + rcc_controller->type = STM32_PERIPHERAL_FIREWALL; + rcc_controller->grant_access = stm32mp25_rcc_grant_access; + + platform_set_drvdata(pdev, rcc_controller); + + ret = stm32_firewall_controller_register(rcc_controller); + if (ret) { + dev_err(dev, "Couldn't register as a firewall controller: %d\n", ret); + return ret; + } + + return 0; +} + +static void stm32mp25_rcc_clocks_remove(struct platform_device *pdev) +{ + struct stm32_firewall_controller *rcc_controller = platform_get_drvdata(pdev); + + stm32_firewall_controller_unregister(rcc_controller); } static struct platform_driver stm32mp25_rcc_clocks_driver = { @@ -1991,6 +2028,7 @@ static struct platform_driver stm32mp25_rcc_clocks_driver = { .of_match_table = stm32mp25_match_data, }, .probe = stm32mp25_rcc_clocks_probe, + .remove = stm32mp25_rcc_clocks_remove, }; static int __init stm32mp25_clocks_init(void) -- 2.43.0