From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 713EB1E411C; Mon, 23 Jun 2025 07:32:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750663950; cv=none; b=k6oz9NB8Gb/DE93RmCUd66F01MVukKCq3CAZNVL1+03ZzTBt2mxvdya8l+/nJNNNplQVriGHciXRqzrlJus/h4r08GZelZxpdHDOazulecIMfnVIeySyA3YPp2w9lsBYHgRBg0H7jwMWUYBqdMXSnM6jn8K36chzLlJ7fltRxJw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750663950; c=relaxed/simple; bh=RLvV0rMPRETp8kXQ1/QLsAR0m2oC5br14HZ07aP+kLY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=SOGPH/jThl0s2YJmAq/ds2xFFlXtpFnZqlVRVJK5bKz95KlSSPhzgx3vNBHsOpTcS/2LoMX2iRp++NkQeswz+nWhHebuVOHHz5i473vys/bGmO2ANTypUcmAtV8ig2RJ/xFrS5QCY/KLQwpmUINaJzRJtTu3L9PNfZIr9XiXACU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=BAoK5jQn; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="BAoK5jQn" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55N6f5ml021145; Mon, 23 Jun 2025 09:32:00 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= vCMmTABrSBqeAhv7e77caexkaudNwZFg/B0FOzQ1fiU=; b=BAoK5jQnku8WmePq n4+L43qX1lNYKbOjX5G8QCpKLxwAQmstCZnuiacM2m+L7CXlwtDeNNrH/GtjiIaT zhkf3Hhus0Cd9rn2wkMOdBff02feboS3AgUPuC817J1cm2e/EHRC3BQnrlXhhwI6 r45v2HebcPgpZ5jJYl8IgOMSNS2uXsvUPSUpW/0kRm195qfOX3oTgLj6HmFC1KaX g8VYmXqEysSiT0TzizJEGHhF89Ozi7J4xJAs0JXLW0+SVffALUXF04hl2+D+7sLf GA9IFh+/1VwpsB9D00WPwvwpJud4vnhkstWB+pxGdvZtYyZzxtLS2UIt0byOP2n2 BtvamA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 47e6a6bxej-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 23 Jun 2025 09:32:00 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6DE8640059; Mon, 23 Jun 2025 09:30:51 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8C7BAB5689E; Mon, 23 Jun 2025 09:29:46 +0200 (CEST) Received: from localhost (10.252.18.29) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 23 Jun 2025 09:29:46 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 23 Jun 2025 09:29:16 +0200 Subject: [PATCH v6 6/8] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp25 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-ID: <20250623-hdp-upstream-v6-6-387536f08398@foss.st.com> References: <20250623-hdp-upstream-v6-0-387536f08398@foss.st.com> In-Reply-To: <20250623-hdp-upstream-v6-0-387536f08398@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , Antonio Borneo CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-c25d1 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-23_02,2025-06-20_01,2025-03-28_01 Add the hdp devicetree node for stm32mp25 SoC family Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 8d87865850a7..fa2b6a1881f2 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1148,6 +1148,13 @@ package_otp@1e8 { }; }; + hdp: pinctrl@44090000 { + compatible = "st,stm32mp251-hdp"; + reg = <0x44090000 0x400>; + clocks = <&rcc CK_BUS_HDP>; + status = "disabled"; + }; + rcc: clock-controller@44200000 { compatible = "st,stm32mp25-rcc"; reg = <0x44200000 0x10000>; -- 2.43.0