[PATCH net-next 0/2] net: dsa: ks8995: Fix up bindings

[PATCH net-next 0/2] net: dsa: ks8995: Fix up bindings

[Linus Walleij]

After looking at the datasheets for KS8995 I realized this is
a DSA switch and need to have DT bindings as such and be implemented
as such.

This series just fixes up the bindings and the offending device tree.

The existing kernel driver which is in drivers/net/phy/spi_ks8995.c
does not implement DSA. It can be forgiven for this because it was
merged in 2011 and the DSA framework was not widely established
back then. It continues to probe fine but needs to be rewritten
to use the special DSA tag and moved to drivers/net/dsa as time
permits. (I hope I can do this.)

It's fine for the networking tree to merge both patches, I maintain
ixp4xx as well. But I can also carry the second patch through the
SoC tree if so desired.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Linus Walleij (2):
      dt-bindings: dsa: Rewrite Micrel KS8995 in schema
      ARM: dts: Fix up wrv54g device tree

 .../devicetree/bindings/net/dsa/micrel,ks8995.yaml | 86 ++++++++++++++++++++++
 .../devicetree/bindings/net/micrel-ks8995.txt      | 20 -----
 .../dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts  | 75 +++++++++++++++----
 3 files changed, 145 insertions(+), 36 deletions(-)
---
base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
change-id: 20250624-ks8995-dsa-bindings-b08348231519

Best regards,
-- 
Linus Walleij <linus.walleij@linaro.org>

[PATCH net-next 1/2] dt-bindings: dsa: Rewrite Micrel KS8995 in schema

[Linus Walleij]

After studying the datasheets for some of the KS8995 variants
it becomes pretty obvious that this is a straight-forward
and simple DSA switch with one port in (CPU) and four outgoing
ports, and it even supports custom tags by setting a bit in
a special register, and elaborate VLAN handling as all DSA
switches do.

Rewrite the terse bindings to YAML, and move to the proper
subdirectory.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 .../devicetree/bindings/net/dsa/micrel,ks8995.yaml | 86 ++++++++++++++++++++++
 .../devicetree/bindings/net/micrel-ks8995.txt      | 20 -----
 2 files changed, 86 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml b/Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..fcecfccbac2bb084db4166539bdd130cdcdae2df
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/micrel,ks8995.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Micrel KS8995 Family DSA Switches
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+description:
+  The Micrel KS8995 DSA Switches were produced in the early-to-mid 2000s.
+  The chip features a CPU port and four outgoing ports, each with an
+  internal PHY. The chip is managed over SPI.
+
+properties:
+  compatible:
+    enum:
+      - micrel,ks8995
+      - micrel,ksz8795
+      - micrel,ksz8864
+
+  reg:
+    maxItems: 1
+
+  reset-gpios:
+    description: GPIO to be used to reset the whole device
+    maxItems: 1
+
+allOf:
+  - $ref: dsa.yaml#/$defs/ethernet-ports
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      ethernet-switch@0 {
+        compatible = "micrel,ks8995";
+        reg = <0>;
+        spi-max-frequency = <25000000>;
+
+        ethernet-ports {
+          #address-cells = <1>;
+          #size-cells = <0>;
+
+          ethernet-port@0 {
+            reg = <0>;
+            label = "lan1";
+          };
+          ethernet-port@1 {
+            reg = <1>;
+            label = "lan2";
+          };
+          ethernet-port@2 {
+            reg = <2>;
+            label = "lan3";
+          };
+          ethernet-port@3 {
+            reg = <3>;
+            label = "lan4";
+          };
+          ethernet-port@4 {
+            reg = <4>;
+            ethernet = <&gmac1>;
+            phy-mode = "rgmii-id";
+            fixed-link {
+              speed = <1000>;
+              full-duplex;
+              pause;
+            };
+          };
+        };
+      };
+    };
diff --git a/Documentation/devicetree/bindings/net/micrel-ks8995.txt b/Documentation/devicetree/bindings/net/micrel-ks8995.txt
deleted file mode 100644
index 281bc2498d12764740dab821e8cabcb5e0a3d8fc..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/net/micrel-ks8995.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Micrel KS8995 SPI controlled Ethernet Switch families
-
-Required properties (according to spi-bus.txt):
-- compatible: either "micrel,ks8995", "micrel,ksz8864" or "micrel,ksz8795"
-
-Optional properties:
-- reset-gpios : phandle of gpio that will be used to reset chip during probe
-
-Example:
-
-spi-master {
-	...
-	switch@0 {
-		compatible = "micrel,ksz8795";
-
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-		reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
-	};
-};

-- 
2.49.0

[PATCH net-next 2/2] ARM: dts: Fix up wrv54g device tree

[Linus Walleij]

Fix up the KS8995 switch and PHYs the way that is most likely:

- Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in
  the outoftree code masks PHYs 1,2,3,4).
- Phy 5 is likely the separate WAN phy directly connected
  to ethc.
- The ethb is probably connected as CPU interface to
  the KS8995.

There are some confused comments in the old board file
replicated into the device tree like ethc being "connected
to port 5 of the ks8995" but this makes no sense as it
is certainly connected to a phy.

Properly integrate the KS8995 switch using the new bindings.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 .../dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts  | 75 +++++++++++++++++-----
 1 file changed, 59 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
index 98275a363c57cde22ef57c3885bc4469677ef790..14b766083e3a870a1154a93be74af6e6738fe137 100644
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
@@ -72,10 +72,50 @@ spi {
 		cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 		num-chipselects = <1>;
 
-		switch@0 {
+		ethernet-switch@0 {
 			compatible = "micrel,ks8995";
 			reg = <0>;
 			spi-max-frequency = <50000000>;
+
+			ethernet-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ethernet-port@0 {
+					reg = <0>;
+					label = "1";
+					phy-mode = "rgmii";
+					phy-handle = <&phy1>;
+				};
+				ethernet-port@1 {
+					reg = <1>;
+					label = "2";
+					phy-mode = "rgmii";
+					phy-handle = <&phy2>;
+				};
+				ethernet-port@2 {
+					reg = <2>;
+					label = "3";
+					phy-mode = "rgmii";
+					phy-handle = <&phy3>;
+				};
+				ethernet-port@3 {
+					reg = <3>;
+					label = "4";
+					phy-mode = "rgmii";
+					phy-handle = <&phy4>;
+				};
+				ethernet-port@4 {
+					reg = <4>;
+					ethernet = <&ethb>;
+					phy-mode = "rgmii-id";
+					fixed-link {
+						speed = <100>;
+						full-duplex;
+					};
+				};
+
+			};
 		};
 	};
 
@@ -134,41 +174,44 @@ pci@c0000000 {
 			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */
 		};
 
-		/*
-		 * EthB - connected to the KS8995 switch ports 1-4
-		 * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
-		 * all four switch ports, also using an out of tree multiphy patch.
-		 * Do we need a new binding and property for this?
-		 */
-		ethernet@c8009000 {
+		ethb: ethernet@c8009000 {
 			status = "okay";
 			queue-rx = <&qmgr 3>;
 			queue-txready = <&qmgr 20>;
-			phy-mode = "rgmii";
-			phy-handle = <&phy4>;
+			phy-mode = "rgmii-id";
+			fixed-link {
+				speed = <100>;
+				full-duplex;
+			};
 
 			mdio {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				/* Should be ports 1-4 on the KS8995 switch */
+				/* Should be LAN ports 1-4 on the KS8995 switch */
+				phy1: ethernet-phy@1 {
+					reg = <1>;
+				};
+				phy2: ethernet-phy@2 {
+					reg = <2>;
+				};
+				phy3: ethernet-phy@3 {
+					reg = <3>;
+				};
 				phy4: ethernet-phy@4 {
 					reg = <4>;
 				};
-
-				/* Should be port 5 on the KS8995 switch */
 				phy5: ethernet-phy@5 {
 					reg = <5>;
 				};
 			};
 		};
 
-		/* EthC - connected to KS8995 switch port 5 */
-		ethernet@c800a000 {
+		ethc: ethernet@c800a000 {
 			status = "okay";
 			queue-rx = <&qmgr 4>;
 			queue-txready = <&qmgr 21>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			phy-handle = <&phy5>;
 		};
 	};

-- 
2.49.0

Re: [PATCH net-next 2/2] ARM: dts: Fix up wrv54g device tree

[Andrew Lunn]

On Tue, Jun 24, 2025 at 09:41:12AM +0200, Linus Walleij wrote:
> Fix up the KS8995 switch and PHYs the way that is most likely:
> 
> - Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in
>   the outoftree code masks PHYs 1,2,3,4).
> - Phy 5 is likely the separate WAN phy directly connected
>   to ethc.
> - The ethb is probably connected as CPU interface to
>   the KS8995.
> 
> There are some confused comments in the old board file
> replicated into the device tree like ethc being "connected
> to port 5 of the ks8995" but this makes no sense as it
> is certainly connected to a phy.
> 
> Properly integrate the KS8995 switch using the new bindings.
> 
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  .../dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts  | 75 +++++++++++++++++-----
>  1 file changed, 59 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
> index 98275a363c57cde22ef57c3885bc4469677ef790..14b766083e3a870a1154a93be74af6e6738fe137 100644
> --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
> +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
> @@ -72,10 +72,50 @@ spi {
>  		cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
>  		num-chipselects = <1>;
>  
> -		switch@0 {
> +		ethernet-switch@0 {
>  			compatible = "micrel,ks8995";
>  			reg = <0>;
>  			spi-max-frequency = <50000000>;
> +
> +			ethernet-ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				ethernet-port@0 {
> +					reg = <0>;
> +					label = "1";
> +					phy-mode = "rgmii";

If this is an internal PHY, it would be better to use 'internal'. I
would like to avoid all the issues around 'rgmii' vs 'rgmii-id'.

> +				ethernet-port@4 {
> +					reg = <4>;
> +					ethernet = <&ethb>;
> +					phy-mode = "rgmii-id";
> +					fixed-link {
> +						speed = <100>;
> +						full-duplex;
> +					};

That is a bit odd, rgmii-id, yet speed limited to 100. It would be
good to add a comment about this.

> @@ -134,41 +174,44 @@ pci@c0000000 {
>  			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */
>  		};
>  
> -		/*
> -		 * EthB - connected to the KS8995 switch ports 1-4
> -		 * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
> -		 * all four switch ports, also using an out of tree multiphy patch.
> -		 * Do we need a new binding and property for this?
> -		 */
> -		ethernet@c8009000 {
> +		ethb: ethernet@c8009000 {
>  			status = "okay";
>  			queue-rx = <&qmgr 3>;
>  			queue-txready = <&qmgr 20>;
> -			phy-mode = "rgmii";
> -			phy-handle = <&phy4>;
> +			phy-mode = "rgmii-id";
> +			fixed-link {
> +				speed = <100>;
> +				full-duplex;
> +			};

This is all confusing. Do you have the board, or a schematic for it? 

Looking at the old DT, this ethernet interface has its own MDIO bus,
with PHYs at address 4 and 5. The phy-handle above means this MAC is
connected to the PHY at address 4. The PHY at address 5 is connected
to the second MAC instance of this SoC. This implies it is:

SOC:MAC-PHY-PHY-MAC:SWITCH 

Rather than the more usual back to back MAC. There are boards with
back to back PHY, so it is not out of the question.

However, it could also be this old DT description is completely
broken, and the PHYs on this bus are the external PHYs for the
switches? There should not be a phy-handle in the MAC nodes.

>  
>  			mdio {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  
> -				/* Should be ports 1-4 on the KS8995 switch */
> +				/* Should be LAN ports 1-4 on the KS8995 switch */
> +				phy1: ethernet-phy@1 {
> +					reg = <1>;
> +				};
> +				phy2: ethernet-phy@2 {
> +					reg = <2>;
> +				};
> +				phy3: ethernet-phy@3 {
> +					reg = <3>;
> +				};
>  				phy4: ethernet-phy@4 {
>  					reg = <4>;
>  				};

This node is the SoC interface MDIO bus. Why would the internal PHYs
of switch bus on the SoC MDIO bus? I would expect the switch to have
its own MDIO bus and place its PHYs there.

	Andrew

Re: [PATCH net-next 2/2] ARM: dts: Fix up wrv54g device tree

[Linus Walleij]

On Tue, Jun 24, 2025 at 10:16 AM Andrew Lunn <andrew@lunn.ch> wrote:
> On Tue, Jun 24, 2025 at 09:41:12AM +0200, Linus Walleij wrote:

> > +                             ethernet-port@0 {
> > +                                     reg = <0>;
> > +                                     label = "1";
> > +                                     phy-mode = "rgmii";
>
> If this is an internal PHY, it would be better to use 'internal'. I
> would like to avoid all the issues around 'rgmii' vs 'rgmii-id'.

OK you're right, I'll rewrite this and the example in the binding
to use "internal", as this is what it is.

The fifth PHY is inside the switch, yet "external" in a way.
They are all managed by external MDIO though, see below.

> > +                             ethernet-port@4 {
> > +                                     reg = <4>;
> > +                                     ethernet = <&ethb>;
> > +                                     phy-mode = "rgmii-id";
> > +                                     fixed-link {
> > +                                             speed = <100>;
> > +                                             full-duplex;
> > +                                     };
>
> That is a bit odd, rgmii-id, yet speed limited to 100. It would be
> good to add a comment about this.

Copy/paste error when working with old code :(

It's good old "mii"

> This is all confusing. Do you have the board, or a schematic for it?

I was confused because I managed to find phonto of thePCB
for the board in question:
https://real.phj.hu/wrv54g/

If you look on the bottom of the image, there is a component
to the LAN ports, chip tag reads: "SWAP net NS604009" (made 0421)
but I think it's just one of these isolation transformers so the
PHYs are indeed internal (the KS8995 is the component above
with the heat sink mounted on top).

> >                       mdio {
> >                               #address-cells = <1>;
> >                               #size-cells = <0>;
> >
> > -                             /* Should be ports 1-4 on the KS8995 switch */
> > +                             /* Should be LAN ports 1-4 on the KS8995 switch */
> > +                             phy1: ethernet-phy@1 {
> > +                                     reg = <1>;
> > +                             };
> > +                             phy2: ethernet-phy@2 {
> > +                                     reg = <2>;
> > +                             };
> > +                             phy3: ethernet-phy@3 {
> > +                                     reg = <3>;
> > +                             };
> >                               phy4: ethernet-phy@4 {
> >                                       reg = <4>;
> >                               };
>
> This node is the SoC interface MDIO bus. Why would the internal PHYs
> of switch bus on the SoC MDIO bus? I would expect the switch to have
> its own MDIO bus and place its PHYs there.

This switch is so old that in difference from other DSA switches it does
not have its own internal MDIO bus... I know for sure because I'm working
on another device and I can access all PHY:s over MDIO. It depends
on an external MDIO connection.

Here is a datasheet:
https://docs.rs-online.com/0889/0900766b81385414.pdf

On page 45 it says:
"A standard MIIM interface is provided for all five PHY devices in the
 KS8995MA/FQ. An external device with MDC/MDIO capability is able
 to read PHY status or to configure PHY settings."

I'll update and repost so it makes more sense!

Yours,
Linus Walleij