[PATCH net-next v2 0/2] net: dsa: ks8995: Fix up bindings

[PATCH net-next v2 0/2] net: dsa: ks8995: Fix up bindings

[Linus Walleij]

After looking at the datasheets for KS8995 I realized this is
a DSA switch and need to have DT bindings as such and be implemented
as such.

This series just fixes up the bindings and the offending device tree.

The existing kernel driver which is in drivers/net/phy/spi_ks8995.c
does not implement DSA. It can be forgiven for this because it was
merged in 2011 and the DSA framework was not widely established
back then. It continues to probe fine but needs to be rewritten
to use the special DSA tag and moved to drivers/net/dsa as time
permits. (I hope I can do this.)

It's fine for the networking tree to merge both patches, I maintain
ixp4xx as well. But I can also carry the second patch through the
SoC tree if so desired.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Changes in v2:
- The device ports are MII and not RGMII (copy/paste error...)
- Document the elusive "port 5" which is a separate PHY inside the
  KS8995 usually used for "WAN" ports in home routers.
- Include a verbose example with a switch-facing ethernet MII and
  a WAN-facing MII for the port 5 PHY in the DT binding.
- Link to v1: https://lore.kernel.org/r/20250624-ks8995-dsa-bindings-v1-0-71a8b4f63315@linaro.org

---
Linus Walleij (2):
      dt-bindings: dsa: Rewrite Micrel KS8995 in schema
      ARM: dts: Fix up wrv54g device tree

 .../devicetree/bindings/net/dsa/micrel,ks8995.yaml | 135 +++++++++++++++++++++
 .../devicetree/bindings/net/micrel-ks8995.txt      |  20 ---
 .../dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts  |  92 +++++++++++---
 3 files changed, 213 insertions(+), 34 deletions(-)
---
base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
change-id: 20250624-ks8995-dsa-bindings-b08348231519

Best regards,
-- 
Linus Walleij <linus.walleij@linaro.org>

[PATCH net-next v2 1/2] dt-bindings: dsa: Rewrite Micrel KS8995 in schema

[Linus Walleij]

After studying the datasheets for some of the KS8995 variants
it becomes pretty obvious that this is a straight-forward
and simple MII DSA switch with one port in (CPU) and four outgoing
ports, and it even supports custom tags by setting a bit in
a special register, and elaborate VLAN handling as all DSA
switches do.

What is a bit odd with KS8995 is that it uses an extra MII-P5
port to access one of the PHYs separately, on the side of the
switch fabric, such as when using a WAN port separately from
a LAN switch in a home router.

Rewrite the terse bindings to YAML, and move to the proper
subdirectory. Include a verbose example to make things clear.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 .../devicetree/bindings/net/dsa/micrel,ks8995.yaml | 135 +++++++++++++++++++++
 .../devicetree/bindings/net/micrel-ks8995.txt      |  20 ---
 2 files changed, 135 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml b/Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..854808ff5ad5d1a607e1e0eb537989351f1f881c
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/micrel,ks8995.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Micrel KS8995 Family DSA Switches
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+description:
+  The Micrel KS8995 DSA Switches are 100 Mbit switches that were produced in
+  the early-to-mid 2000s. The chip features a CPU port and four outgoing ports,
+  each with an internal PHY. The chip itself is managed over SPI, but all the
+  PHYs need to be accessed from an external MDIO channel.
+
+  Further, a fifth PHY is available and can be used separately from the switch
+  fabric, connected to an external MII interface name MII-P5. This is
+  unrelated from the CPU-facing port 5 which is used for DSA MII traffic.
+
+properties:
+  compatible:
+    enum:
+      - micrel,ks8995
+      - micrel,ksz8795
+      - micrel,ksz8864
+
+  reg:
+    maxItems: 1
+
+  reset-gpios:
+    description: GPIO to be used to reset the whole device
+    maxItems: 1
+
+allOf:
+  - $ref: dsa.yaml#/$defs/ethernet-ports
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      ethernet-switch@0 {
+        compatible = "micrel,ks8995";
+        reg = <0>;
+        spi-max-frequency = <25000000>;
+
+        ethernet-ports {
+          #address-cells = <1>;
+          #size-cells = <0>;
+
+          ethernet-port@0 {
+            reg = <0>;
+            label = "lan1";
+          };
+          ethernet-port@1 {
+            reg = <1>;
+            label = "lan2";
+          };
+          ethernet-port@2 {
+            reg = <2>;
+            label = "lan3";
+          };
+          ethernet-port@3 {
+            reg = <3>;
+            label = "lan4";
+          };
+          ethernet-port@4 {
+            reg = <4>;
+            ethernet = <&mac2>;
+            phy-mode = "mii";
+            fixed-link {
+              speed = <100>;
+              full-duplex;
+            };
+          };
+        };
+      };
+    };
+
+    soc {
+      #address-cells = <1>;
+      #size-cells = <1>;
+
+      /* The WAN port connected on MII-P5 */
+      ethernet-port@1000 {
+        reg = <0x00001000 0x1000>;
+        label = "wan";
+        phy-mode = "mii";
+        phy-handle = <&phy5>;
+      };
+
+      mac2: ethernet-port@2000 {
+        reg = <0x00002000 0x1000>;
+        phy-mode = "mii";
+        fixed-link {
+          speed = <100>;
+          full-duplex;
+        };
+      };
+    };
+
+    mdio {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      /* LAN PHYs 1-4 accessible over external MDIO */
+      phy1: ethernet-phy@1 {
+        reg = <1>;
+      };
+      phy2: ethernet-phy@2 {
+        reg = <2>;
+      };
+      phy3: ethernet-phy@3 {
+        reg = <3>;
+      };
+      phy4: ethernet-phy@4 {
+        reg = <4>;
+      };
+      /* WAN PHY accessible over external MDIO */
+      phy5: ethernet-phy@5 {
+        reg = <5>;
+      };
+    };
diff --git a/Documentation/devicetree/bindings/net/micrel-ks8995.txt b/Documentation/devicetree/bindings/net/micrel-ks8995.txt
deleted file mode 100644
index 281bc2498d12764740dab821e8cabcb5e0a3d8fc..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/net/micrel-ks8995.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Micrel KS8995 SPI controlled Ethernet Switch families
-
-Required properties (according to spi-bus.txt):
-- compatible: either "micrel,ks8995", "micrel,ksz8864" or "micrel,ksz8795"
-
-Optional properties:
-- reset-gpios : phandle of gpio that will be used to reset chip during probe
-
-Example:
-
-spi-master {
-	...
-	switch@0 {
-		compatible = "micrel,ksz8795";
-
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-		reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
-	};
-};

-- 
2.49.0

Re: [PATCH net-next v2 1/2] dt-bindings: dsa: Rewrite Micrel KS8995 in schema

[Andrew Lunn]

On Wed, Jun 25, 2025 at 08:51:24AM +0200, Linus Walleij wrote:
> After studying the datasheets for some of the KS8995 variants
> it becomes pretty obvious that this is a straight-forward
> and simple MII DSA switch with one port in (CPU) and four outgoing
> ports, and it even supports custom tags by setting a bit in
> a special register, and elaborate VLAN handling as all DSA
> switches do.
> 
> What is a bit odd with KS8995 is that it uses an extra MII-P5
> port to access one of the PHYs separately, on the side of the
> switch fabric, such as when using a WAN port separately from
> a LAN switch in a home router.
> 
> Rewrite the terse bindings to YAML, and move to the proper
> subdirectory. Include a verbose example to make things clear.
> 
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The way this 5th PHY is used is different to any other switch i have
seen. By following phandles, i think there is enough information to
work out how to configure it.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v2 1/2] dt-bindings: dsa: Rewrite Micrel KS8995 in schema

[Rob Herring (Arm)]

On Wed, 25 Jun 2025 08:51:24 +0200, Linus Walleij wrote:
> After studying the datasheets for some of the KS8995 variants
> it becomes pretty obvious that this is a straight-forward
> and simple MII DSA switch with one port in (CPU) and four outgoing
> ports, and it even supports custom tags by setting a bit in
> a special register, and elaborate VLAN handling as all DSA
> switches do.
> 
> What is a bit odd with KS8995 is that it uses an extra MII-P5
> port to access one of the PHYs separately, on the side of the
> switch fabric, such as when using a WAN port separately from
> a LAN switch in a home router.
> 
> Rewrite the terse bindings to YAML, and move to the proper
> subdirectory. Include a verbose example to make things clear.
> 
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  .../devicetree/bindings/net/dsa/micrel,ks8995.yaml | 135 +++++++++++++++++++++
>  .../devicetree/bindings/net/micrel-ks8995.txt      |  20 ---
>  2 files changed, 135 insertions(+), 20 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH net-next v2 2/2] ARM: dts: Fix up wrv54g device tree

[Linus Walleij]

Fix up the KS8995 switch and PHYs the way that is most likely:

- Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in
  the outoftree code masks PHYs 1,2,3,4).
- Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly
  connected to EthC.
- The EthB MII is probably connected as CPU interface to the
  KS8995.

Properly integrate the KS8995 switch using the new bindings.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 .../dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts  | 92 ++++++++++++++++++----
 1 file changed, 78 insertions(+), 14 deletions(-)

diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
index 98275a363c57cde22ef57c3885bc4469677ef790..cb1842c83ac8edc311ea30515f2e9c97f303cf17 100644
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
@@ -72,10 +72,55 @@ spi {
 		cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 		num-chipselects = <1>;
 
-		switch@0 {
+		ethernet-switch@0 {
 			compatible = "micrel,ks8995";
 			reg = <0>;
 			spi-max-frequency = <50000000>;
+
+			/*
+			 * The PHYs are accessed over the external MDIO
+			 * bus and not internally through the switch control
+			 * registers.
+			 */
+			ethernet-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ethernet-port@0 {
+					reg = <0>;
+					label = "1";
+					phy-mode = "mii";
+					phy-handle = <&phy1>;
+				};
+				ethernet-port@1 {
+					reg = <1>;
+					label = "2";
+					phy-mode = "mii";
+					phy-handle = <&phy2>;
+				};
+				ethernet-port@2 {
+					reg = <2>;
+					label = "3";
+					phy-mode = "mii";
+					phy-handle = <&phy3>;
+				};
+				ethernet-port@3 {
+					reg = <3>;
+					label = "4";
+					phy-mode = "mii";
+					phy-handle = <&phy4>;
+				};
+				ethernet-port@4 {
+					reg = <4>;
+					ethernet = <&ethb>;
+					phy-mode = "mii";
+					fixed-link {
+						speed = <100>;
+						full-duplex;
+					};
+				};
+
+			};
 		};
 	};
 
@@ -135,40 +180,59 @@ pci@c0000000 {
 		};
 
 		/*
-		 * EthB - connected to the KS8995 switch ports 1-4
-		 * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
-		 * all four switch ports, also using an out of tree multiphy patch.
-		 * Do we need a new binding and property for this?
+		 * EthB connects to the KS8995 CPU port and faces ports 1-4
+		 * through the switch fabric.
+		 *
+		 * To complicate things, the MDIO channel is also only
+		 * accessible through EthB, but used independently for PHY
+		 * control.
 		 */
-		ethernet@c8009000 {
+		ethb: ethernet@c8009000 {
 			status = "okay";
 			queue-rx = <&qmgr 3>;
 			queue-txready = <&qmgr 20>;
-			phy-mode = "rgmii";
-			phy-handle = <&phy4>;
+			phy-mode = "mii";
+			fixed-link {
+				speed = <100>;
+				full-duplex;
+			};
 
 			mdio {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				/* Should be ports 1-4 on the KS8995 switch */
+				/*
+				 * LAN ports 1-4 on the KS8995 switch
+				 * and PHY5 for WAN need to be accessed
+				 * through this external MDIO channel.
+				 */
+				phy1: ethernet-phy@1 {
+					reg = <1>;
+				};
+				phy2: ethernet-phy@2 {
+					reg = <2>;
+				};
+				phy3: ethernet-phy@3 {
+					reg = <3>;
+				};
 				phy4: ethernet-phy@4 {
 					reg = <4>;
 				};
-
-				/* Should be port 5 on the KS8995 switch */
 				phy5: ethernet-phy@5 {
 					reg = <5>;
 				};
 			};
 		};
 
-		/* EthC - connected to KS8995 switch port 5 */
-		ethernet@c800a000 {
+		/*
+		 * EthC connects to MII-P5 on the KS8995 bypassing
+		 * all of the switch logic and facing PHY5
+		 */
+		ethc: ethernet@c800a000 {
 			status = "okay";
 			queue-rx = <&qmgr 4>;
 			queue-txready = <&qmgr 21>;
-			phy-mode = "rgmii";
+			phy-mode = "mii";
 			phy-handle = <&phy5>;
 		};
 	};

-- 
2.49.0

Re: [PATCH net-next v2 2/2] ARM: dts: Fix up wrv54g device tree

[Andrew Lunn]

On Wed, Jun 25, 2025 at 08:51:25AM +0200, Linus Walleij wrote:
> Fix up the KS8995 switch and PHYs the way that is most likely:
> 
> - Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in
>   the outoftree code masks PHYs 1,2,3,4).
> - Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly
>   connected to EthC.
> - The EthB MII is probably connected as CPU interface to the
>   KS8995.
> 
> Properly integrate the KS8995 switch using the new bindings.
> 
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v2 0/2] net: dsa: ks8995: Fix up bindings

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:

On Wed, 25 Jun 2025 08:51:23 +0200 you wrote:
> After looking at the datasheets for KS8995 I realized this is
> a DSA switch and need to have DT bindings as such and be implemented
> as such.
> 
> This series just fixes up the bindings and the offending device tree.
> 
> The existing kernel driver which is in drivers/net/phy/spi_ks8995.c
> does not implement DSA. It can be forgiven for this because it was
> merged in 2011 and the DSA framework was not widely established
> back then. It continues to probe fine but needs to be rewritten
> to use the special DSA tag and moved to drivers/net/dsa as time
> permits. (I hope I can do this.)
> 
> [...]

Here is the summary with links:
  - [net-next,v2,1/2] dt-bindings: dsa: Rewrite Micrel KS8995 in schema
    https://git.kernel.org/netdev/net-next/c/a0f29a07b654
  - [net-next,v2,2/2] ARM: dts: Fix up wrv54g device tree
    https://git.kernel.org/netdev/net-next/c/c9cc6b6a7d23

You are awesome, thank you!
-- 
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