From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 802FD21421A for ; Thu, 26 Jun 2025 02:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750905446; cv=none; b=tpaWr90pX7qDwJkv60BmTLj/JU7V267vFprvayTDtkKPnBz4eEbImd+aPgdcn7KMTDqGHiYPK5Kjz8rNQcJDWA2O19rHdj/TAqU0DUDGqS1oULYZy9ezunUtvbvTofWVQG5bayEN+8uJ6Cv9iBuPZc4qmVHubSDzwxCYchmcfLo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750905446; c=relaxed/simple; bh=yWtCCxpMNPD3uS3Bi7H/Hp18Cho/E9Z77Yln+Cm21OE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=W9e8z373ppHfooo5devDDlIb6wOxBWnOffy9MpOGTLKC8rnLjHRAaPVaRfwgrLB/WUCqmoIhQXG38WoRifkBhnabbH+YanqKFXFpbk9dZgS32i4YOarZwvmV0IVi2km1f9zy46iioyzwkdIH/4M59UM8nvyV4rkAK8SvJCDiV38= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=XFthsoYh; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="XFthsoYh" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250626023723epoutp030954494d272d92b6f208fd906e13a457~MdzlGQEPs1713317133epoutp03f for ; Thu, 26 Jun 2025 02:37:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250626023723epoutp030954494d272d92b6f208fd906e13a457~MdzlGQEPs1713317133epoutp03f DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1750905443; bh=9jzUBK4rfaWiMXa828Ff+bfipS/KVj9eyi+oP2TMhHY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XFthsoYhxPVBZGIn4ijlvQNek8TKNJelMJMeyFEhhavzpoDc6kfiWhcdk6fyYZD8Q Ytevyj9Q2Codlab+gL6zX33Mizb1yq3jMlSvBZrNK9pHUC4063pb/9XAznWFoLVELO vfr4QYNoAkg4dkU7UMdM+3pUAKdb7EYwajTNg0hM= Received: from epsnrtp04.localdomain (unknown [182.195.42.156]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250626023722epcas5p36a5140741b9bd88cc7b90a44f9c9d3a8~MdzkMXEq-0375103751epcas5p34; Thu, 26 Jun 2025 02:37:22 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.179]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4bSNBR5LsWz6B9m7; Thu, 26 Jun 2025 02:37:19 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250625165258epcas5p4ddbbcfa60703f3682b94ae4eb814da7e~MV1UxW_BP0913509135epcas5p4s; Wed, 25 Jun 2025 16:52:58 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250625165255epsmtip289f7380990344ec0cb7618be15119205~MV1R5dbAo1750917509epsmtip2I; Wed, 25 Jun 2025 16:52:55 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-fsd@tesla.com Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi , Hrishikesh Dileep Subject: [PATCH v2 03/10] PCI: exynos: Reorder MACROs to maintain consistency Date: Wed, 25 Jun 2025 22:22:22 +0530 Message-ID: <20250625165229.3458-4-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250625165229.3458-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20250625165258epcas5p4ddbbcfa60703f3682b94ae4eb814da7e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250625165258epcas5p4ddbbcfa60703f3682b94ae4eb814da7e References: <20250625165229.3458-1-shradha.t@samsung.com> Exynos PCI file follows MACRO definition order where register offset is defined in ascending order and each bit field within the offset is defined right after offset definition. Some MACROs are out of order and so reorder those MACROs to maintain consistency. Suggested-by: Hrishikesh Dileep Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index 30d12ff9b0c6..b4ec167b0583 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -27,11 +27,11 @@ /* PCIe ELBI registers */ #define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_IRQ_INTA_ASSERT BIT(0) #define EXYNOS_IRQ_INTB_ASSERT BIT(2) #define EXYNOS_IRQ_INTC_ASSERT BIT(4) #define EXYNOS_IRQ_INTD_ASSERT BIT(6) -#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 #define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 #define EXYNOS_PCIE_SW_WAKE 0x018 @@ -42,9 +42,9 @@ #define EXYNOS_PCIE_NONSTICKY_RESET 0x024 #define EXYNOS_PCIE_APP_INIT_RESET 0x028 #define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 #define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 #define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) -#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 #define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) -- 2.49.0