* [PATCHv4] dt-bindings: net: convert socfpga-dwmac.txt to DT schema
@ 2025-06-24 19:15 Dinh Nguyen
2025-06-26 19:09 ` Rob Herring (Arm)
0 siblings, 1 reply; 3+ messages in thread
From: Dinh Nguyen @ 2025-06-24 19:15 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowskii+dt, conor+dt; +Cc: dinguyen, devicetree
Convert the socfpga-dwmac.txt to yaml.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v4: remove maxItems for clock-names
v3: Address all of Rob Herring's comments
v2: Add allOf to include the base dmac yaml
fix Rob Herring's dt_binding_check warnings
---
.../bindings/net/altr,dwmac-socfpga.yaml | 138 ++++++++++++++++++
.../devicetree/bindings/net/socfpga-dwmac.txt | 57 --------
2 files changed, 138 insertions(+), 57 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml
delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
diff --git a/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml b/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml
new file mode 100644
index 000000000000..e852d282d37a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/altr,dwmac-socfpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel/Altera SoCFPGA DWMAC controller
+
+maintainers:
+ - Dinh Nguyen <dinguyen@kernel.org>
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - altr,socfpga-stmmac
+ - altr,socfpga-stmmac-a10-s10
+ required:
+ - compatible
+
+allOf:
+ - $ref: snps,dwmac.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: altr,socfpga-stmmac
+ - const: snps,dwmac-3.70a
+ - const: snps,dwmac
+ - items:
+ - const: altr,socfpga-stmmac-a10-s10
+ - const: snps,dwmac-3.72a
+ - const: snps,dwmac
+ - items:
+ - const: altr,socfpga-stmmac-a10-s10
+ - const: snps,dwmac-3.74a
+ - const: snps,dwmac
+
+ reg:
+ maxItems: 1
+
+ iommus:
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ minItems: 1
+ items:
+ - description: GMAC main clock
+ - description: PTP clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: stmmaceth
+ - const: ptp_ref
+
+ resets:
+ minItems: 1
+ items:
+ - description: GMAC stmmaceth reset
+ - description: AHB reset
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: stmmaceth
+ - const: ahb
+
+ interrupts:
+ items:
+ - description: DWMAC interrupt
+
+ interrupt-names:
+ items:
+ - const: macirq
+
+ phy-mode:
+ maxItems: 1
+ items:
+ enum:
+ - rgmii
+ - gmii
+ - mii
+
+ altr,sysmgr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the sysmgr node
+ - description: register offset that controls the SDMMC clock phase
+ - description: register shift for the smplsel(drive in) setting
+ description:
+ Should be the phandle to the system manager node that
+ encompasses the glue register, the register offset, and the register shift.
+ On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
+ on the Arria10/Stratix10/Agilex platforms, the register shift represents
+ bit for each emac to enable/disable signals from the FPGA fabric to the
+ EMAC modules.
+
+ altr,emac-splitter:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should be the phandle to the emac splitter soft IP node if DWMAC
+ controller is connected emac splitter.
+
+ altr,sgmii-to-sgmii-converter:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the TSE SGMII converter.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phy-mode
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ gmac0: ethernet@ff700000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+ reg = <0xff700000 0x2000>;
+ interrupts = <0 115 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+ clocks = <&emac_0_clk>;
+ clock-names = "stmmaceth";
+ phy-mode = "rgmii";
+ tx-fifo-depth = <16384>;
+ rx-fifo-depth = <16384>;
+ };
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
deleted file mode 100644
index 612a8e8abc88..000000000000
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-Altera SOCFPGA SoC DWMAC controller
-
-This is a variant of the dwmac/stmmac driver an inherits all descriptions
-present in Documentation/devicetree/bindings/net/stmmac.txt.
-
-The device node has additional properties:
-
-Required properties:
- - compatible : For Cyclone5/Arria5 SoCs it should contain
- "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
- "altr,socfpga-stmmac-a10-s10".
- Along with "snps,dwmac" and any applicable more detailed
- designware version numbers documented in stmmac.txt
- - altr,sysmgr-syscon : Should be the phandle to the system manager node that
- encompasses the glue register, the register offset, and the register shift.
- On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
- on the Arria10/Stratix10/Agilex platforms, the register shift represents
- bit for each emac to enable/disable signals from the FPGA fabric to the
- EMAC modules.
- - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
- for ptp ref clk. This affects all emacs as the clock is common.
-
-Optional properties:
-altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
- DWMAC controller is connected emac splitter.
-phy-mode: The phy mode the ethernet operates in
-altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
-
-This device node has additional phandle dependency, the sgmii converter:
-
-Required properties:
- - compatible : Should be altr,gmii-to-sgmii-2.0
- - reg-names : Should be "eth_tse_control_port"
-
-Example:
-
-gmii_to_sgmii_converter: phy@100000240 {
- compatible = "altr,gmii-to-sgmii-2.0";
- reg = <0x00000001 0x00000240 0x00000008>,
- <0x00000001 0x00000200 0x00000040>;
- reg-names = "eth_tse_control_port";
- clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
- clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
-};
-
-gmac0: ethernet@ff700000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x60 0>;
- reg = <0xff700000 0x2000>;
- interrupts = <0 115 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_0_clk>;
- clock-names = "stmmaceth";
- phy-mode = "sgmii";
- altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
-};
--
2.42.0.411.g813d9a9188
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCHv4] dt-bindings: net: convert socfpga-dwmac.txt to DT schema
2025-06-24 19:15 [PATCHv4] dt-bindings: net: convert socfpga-dwmac.txt to DT schema Dinh Nguyen
@ 2025-06-26 19:09 ` Rob Herring (Arm)
2025-06-26 23:49 ` Rob Herring
0 siblings, 1 reply; 3+ messages in thread
From: Rob Herring (Arm) @ 2025-06-26 19:09 UTC (permalink / raw)
To: Dinh Nguyen; +Cc: devicetree, krzysztof.kozlowskii+dt, robh+dt, conor+dt
On Tue, 24 Jun 2025 14:15:49 -0500, Dinh Nguyen wrote:
> Convert the socfpga-dwmac.txt to yaml.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v4: remove maxItems for clock-names
> v3: Address all of Rob Herring's comments
> v2: Add allOf to include the base dmac yaml
> fix Rob Herring's dt_binding_check warnings
> ---
> .../bindings/net/altr,dwmac-socfpga.yaml | 138 ++++++++++++++++++
> .../devicetree/bindings/net/socfpga-dwmac.txt | 57 --------
> 2 files changed, 138 insertions(+), 57 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml
> delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCHv4] dt-bindings: net: convert socfpga-dwmac.txt to DT schema
2025-06-26 19:09 ` Rob Herring (Arm)
@ 2025-06-26 23:49 ` Rob Herring
0 siblings, 0 replies; 3+ messages in thread
From: Rob Herring @ 2025-06-26 23:49 UTC (permalink / raw)
To: Dinh Nguyen; +Cc: devicetree, krzysztof.kozlowskii+dt, conor+dt
On Thu, Jun 26, 2025 at 02:09:46PM -0500, Rob Herring (Arm) wrote:
>
> On Tue, 24 Jun 2025 14:15:49 -0500, Dinh Nguyen wrote:
> > Convert the socfpga-dwmac.txt to yaml.
> >
> > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> > ---
> > v4: remove maxItems for clock-names
> > v3: Address all of Rob Herring's comments
> > v2: Add allOf to include the base dmac yaml
> > fix Rob Herring's dt_binding_check warnings
> > ---
> > .../bindings/net/altr,dwmac-socfpga.yaml | 138 ++++++++++++++++++
> > .../devicetree/bindings/net/socfpga-dwmac.txt | 57 --------
> > 2 files changed, 138 insertions(+), 57 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/net/altr,dwmac-socfpga.yaml
> > delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
> >
>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Unreviewed... There's also this conversion[1] which came first and is
more complete. Please comment on it.
Rob
[1] https://lore.kernel.org/all/20250613225844.43148-1-matthew.gerlach@altera.com/
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-06-26 23:49 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-24 19:15 [PATCHv4] dt-bindings: net: convert socfpga-dwmac.txt to DT schema Dinh Nguyen
2025-06-26 19:09 ` Rob Herring (Arm)
2025-06-26 23:49 ` Rob Herring
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).