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From: Krzysztof Kozlowski <krzk@kernel.org>
To: hans.zhang@cixtech.com
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
	 mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org,
	krzk+dt@kernel.org,  conor+dt@kernel.org, mpillai@cadence.com,
	fugang.duan@cixtech.com,  guoyin.chen@cixtech.com,
	peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com,
	 linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1
Date: Mon, 30 Jun 2025 09:33:15 +0200	[thread overview]
Message-ID: <20250630-proficient-fearless-rottweiler-efde37@krzk-bin> (raw)
In-Reply-To: <20250630041601.399921-14-hans.zhang@cixtech.com>

On Mon, Jun 30, 2025 at 12:16:00PM +0800, hans.zhang@cixtech.com wrote:
> From: Hans Zhang <hans.zhang@cixtech.com>
> 
> Add pcie_x*_rc node to support Sky1 PCIe driver based on the
> Cadence PCIe core.
> 
> Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts
> using the ARM GICv3.
> 
> Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
> Reviewed-by: Peter Chen <peter.chen@cixtech.com>
> Reviewed-by: Manikandan K Pillai <mpillai@cadence.com>

Where?

> ---
>  arch/arm64/boot/dts/cix/sky1.dtsi | 150 ++++++++++++++++++++++++++++++
>  1 file changed, 150 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> index 9c723917d8ca..1dac0e8d5fc1 100644
> --- a/arch/arm64/boot/dts/cix/sky1.dtsi
> +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
> @@ -289,6 +289,156 @@ mbox_ap2sfh: mailbox@80a0000 {
>  			cix,mbox-dir = "tx";
>  		};
>  
> +		pcie_x8_rc: pcie@a010000 { /* X8 */
> +			compatible = "cix,sky1-pcie-host";
> +			reg = <0x00 0x0a010000 0x00 0x10000>,
> +			      <0x00 0x0a000000 0x00 0x10000>,
> +			      <0x00 0x2c000000 0x00 0x4000000>,
> +			      <0x00 0x60000000 0x00 0x00100000>;
> +			reg-names = "reg", "rcsu", "cfg", "msg";
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
> +			max-link-speed = <4>;
> +			num-lanes = <8>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			bus-range = <0xc0 0xff>;
> +			device_type = "pci";
> +			ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>,
> +				 <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>,
> +				 <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;

And none of the two reviewers asked you to follow DTS coding style? If
reviewer knows not much about DTS, don't review. Add an ack or
something, dunno, or actually perform proper review.

Best regards,
Krzysztof


  reply	other threads:[~2025-06-30  7:33 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-30  4:15 [PATCH v5 00/14] Enhance the PCIe controller driver hans.zhang
2025-06-30  4:15 ` [PATCH v5 01/14] dt-bindings: pci: cadence: Extend compatible for new RP configuration hans.zhang
2025-06-30  7:30   ` Krzysztof Kozlowski
2025-06-30  8:02     ` Hans Zhang
2025-06-30  8:06       ` Manikandan Karunakaran Pillai
2025-06-30 11:11         ` Krzysztof Kozlowski
2025-07-01 11:56           ` Manikandan Karunakaran Pillai
2025-07-02 20:20             ` Krzysztof Kozlowski
2025-07-03  1:35               ` Manikandan Karunakaran Pillai
2025-07-03  6:55                 ` Krzysztof Kozlowski
2025-06-30  4:15 ` [PATCH v5 02/14] dt-bindings: pci: cadence: Extend compatible for new EP configuration hans.zhang
2025-06-30  7:27   ` Krzysztof Kozlowski
2025-06-30  8:03     ` Hans Zhang
2025-06-30 10:28   ` Krzysztof Kozlowski
2025-06-30  4:15 ` [PATCH v5 03/14] PCI: cadence: Split PCIe controller header file hans.zhang
2025-06-30  4:15 ` [PATCH v5 04/14] PCI: cadence: Add register definitions for HPA(High Perf Architecture) hans.zhang
2025-06-30  4:15 ` [PATCH v5 05/14] PCI: cadence: Split PCIe EP support into common and specific functions hans.zhang
2025-06-30  4:15 ` [PATCH v5 06/14] PCI: cadence: Split PCIe RP " hans.zhang
2025-06-30  4:15 ` [PATCH v5 07/14] PCI: cadence: Split the common functions for PCIE controller support hans.zhang
2025-06-30  4:15 ` [PATCH v5 08/14] PCI: cadence: Add support for High Performance Arch(HPA) controller hans.zhang
2025-06-30  4:15 ` [PATCH v5 09/14] PCI: cadence: Add support for PCIe HPA controller platform hans.zhang
2025-06-30  4:15 ` [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-06-30  5:36   ` Rob Herring (Arm)
2025-06-30  5:56     ` Hans Zhang
2025-06-30  7:26   ` Krzysztof Kozlowski
2025-06-30  8:29     ` Hans Zhang
2025-06-30 11:14       ` Krzysztof Kozlowski
2025-06-30 15:30         ` Hans Zhang
2025-07-02 20:23           ` Krzysztof Kozlowski
2025-07-03  1:47             ` Hans Zhang
2025-07-14  7:43               ` Krzysztof Kozlowski
2025-07-14  8:03                 ` Hans Zhang
2025-07-15  6:40                   ` Krzysztof Kozlowski
2025-07-15  6:46                     ` Hans Zhang
2025-06-30 15:54     ` Hans Zhang
2025-07-02 20:28       ` Krzysztof Kozlowski
2025-06-30  4:15 ` [PATCH v5 11/14] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-06-30  4:15 ` [PATCH v5 12/14] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-06-30  7:29   ` Krzysztof Kozlowski
2025-06-30  8:06     ` Hans Zhang
2025-06-30  4:16 ` [PATCH v5 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-06-30  7:33   ` Krzysztof Kozlowski [this message]
2025-06-30  8:44     ` Hans Zhang
2025-06-30  4:16 ` [PATCH v5 14/14] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-06-30  7:32   ` Krzysztof Kozlowski
2025-06-30  8:08     ` Hans Zhang

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