[PATCH v5 0/8] add Voyager board support

Ben Zong-You Xie
2025-06-02T06:08:57Z

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
including Andes QiLai SoC. This patch series adds minimal device tree
files for the QiLai SoC and the Voyager board [1].

Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
---
Changelog from v4 to v5:
- Rebase the series on torvalds/master
- Clarify the patch dependencies (2 <- 4 <- 5 <- 6) in the patch description

v4: https://lore.kernel.org/all/20250514095350.3765716-1-ben717@andestech.com/

Changelog from v3 to v4:
- Restore the modification to cache-sets and cache-size in patch 6
- Do not constrain renesas,r9a07g043f-ax45mp-cache since it's independent to
this series.
- Delete the redundant example added by patch 6

v3: https://lore.kernel.org/all/20250513094933.1631493-1-ben717@andestech.com/

Changelog from v2 to v3:
- Rebase the series on Conor/riscv-soc-for-next
- Reform patch 6 as suggested by Conor
- Modify l2_cache's compatible in qilai.dtsi due to patch 6
- Add Conor's Acked-by tag to patch 4
- Add Conor's Acked-by tag to patch 5
- Add Conor's Acked-by tag to patch 9

v2: https://lore.kernel.org/all/20250503151829.605006-5-ben717@andestech.com/

Changelog from v1 to v2:
- Add detailed descriptions to PLIC_SW and PLMT0
- Move the aliases node and memory node from qilai.dtsi to qilai-voyager.dts
- Drop "status = okay" in each CPU node since the status property is by
default "okay"
- Reorder the nodes in qilai.dtsi by unit address in ascending order
- Add myself as the maintainer of Andes's SoC tree
- Add Rob's Reviewed-by tag to patch 2
- Add Rob's Acked-by tag to patch 3
- Add Rob's Acked-by tag to patch 6.

v1: https://lore.kernel.org/all/20250407104937.315783-1-ben717@andestech.com/

---
Ben Zong-You Xie (8):
riscv: add Andes SoC family Kconfig support
dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
dt-bindings: interrupt-controller: add Andes QiLai PLIC
dt-bindings: interrupt-controller: add Andes machine-level software
interrupt controller
dt-bindings: timer: add Andes machine timer
riscv: dts: andes: add QiLai SoC device tree
riscv: dts: andes: add Voyager board device tree
riscv: defconfig: enable Andes SoC

.../andestech,plicsw.yaml | 54 +++++
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/andes.yaml | 25 +++
.../bindings/timer/andestech,plmt0.yaml | 53 +++++
MAINTAINERS | 9 +
arch/riscv/Kconfig.errata | 2 +-
arch/riscv/Kconfig.socs | 9 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/andes/Makefile | 2 +
arch/riscv/boot/dts/andes/qilai-voyager.dts | 28 +++
arch/riscv/boot/dts/andes/qilai.dtsi | 186 ++++++++++++++++++
arch/riscv/configs/defconfig | 1 +
12 files changed, 370 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
create mode 100644 arch/riscv/boot/dts/andes/Makefile
create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts
create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi

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2.34.1