[PATCH v5 1/8] riscv: add Andes SoC family Kconfig support

Ben Zong-You Xie
2025-06-02T06:08:57Z

The first SoC in the Andes series is QiLai. It includes a high-performance
quad-core RISC-V AX45MP cluster and one NX27V vector processor.

For further information, refer to [1].

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
arch/riscv/Kconfig.errata | 2 +-
arch/riscv/Kconfig.socs | 9 +++++++++
2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index e318119d570d..be76883704a6 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -12,7 +12,7 @@ config ERRATA_ANDES

config ERRATA_ANDES_CMO
bool "Apply Andes cache management errata"
- depends on ERRATA_ANDES && ARCH_R9A07G043
+ depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
select RISCV_DMA_NONCOHERENT
default y
help
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 8b503e54fa1b..2f1626daaad1 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,14 @@
menu "SoC selection"

+config ARCH_ANDES
+ bool "Andes SoCs"
+ depends on MMU && !XIP_KERNEL
+ select ERRATA_ANDES
+ select ERRATA_ANDES_CMO
+ select AX45MP_L2_CACHE
+ help
+ This enables support for Andes SoC platform hardware.
+
config ARCH_MICROCHIP_POLARFIRE
def_bool ARCH_MICROCHIP

--
2.34.1