[PATCH v5 4/8] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller

Ben Zong-You Xie
2025-06-02T06:08:15Z

Add the DT binding documentation for Andes machine-level software
interrupt controller.

In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
second time with all interrupt sources tied to zero as the software
interrupt controller (PLICSW). PLICSW can generate machine-level software
interrupts through programming its registers.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
This patch depends on patch 2
---
.../andestech,plicsw.yaml | 54 +++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
new file mode 100644
index 000000000000..eb2eb611ac09
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes machine-level software interrupt controller
+
+description:
+ In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
+ second time with all interrupt sources tied to zero as the software interrupt
+ controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
+ inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
+ controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
+ generate machine-mode inter-processor interrupts through programming its
+ registers.
+
+maintainers:
+ - Ben Zong-You Xie <ben717@andestech.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - andestech,qilai-plicsw
+ - const: andestech,plicsw
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 15872
+ description:
+ Specifies which harts are connected to the PLIC_SW. Each item must points
+ to a riscv,cpu-intc node, which has a riscv cpu node as parent.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ interrupt-controller@400000 {
+ compatible = "andestech,qilai-plicsw", "andestech,plicsw";
+ reg = <0x400000 0x400000>;
+ interrupts-extended = <&cpu0intc 3>,
+ <&cpu1intc 3>,
+ <&cpu2intc 3>,
+ <&cpu3intc 3>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3777a6e83a6b..b79cdd43fe37 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20950,6 +20950,7 @@ F: include/linux/irqchip/riscv-imsic.h
RISC-V ANDES SoC Support
M: Ben Zong-You Xie <ben717@andestech.com>
S: Maintained
+F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
F: Documentation/devicetree/bindings/riscv/andes.yaml

RISC-V ARCHITECTURE
--
2.34.1