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Thu, 3 Jul 2025 03:38:51 -0700 From: Sumit Gupta To: , , , , , , , CC: , , Subject: [PATCH v2 3/8] soc: tegra: cbb: make error interrupt enable and status per SoC Date: Thu, 3 Jul 2025 16:08:24 +0530 Message-ID: <20250703103829.1721024-4-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250703103829.1721024-1-sumitg@nvidia.com> References: <20250703103829.1721024-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026369:EE_|DM4PR12MB6615:EE_ X-MS-Office365-Filtering-Correlation-Id: 4150f4cc-5c63-4407-b6c1-08ddba1dd643 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?K2s0S/7dXKo0vYpnCRR68knV6TpJJSZdRdl09TYgUtGFXofabXtOLho0z2uC?= =?us-ascii?Q?u0AEeIAXlade9YhKWXMXh6GM9fnVJ0t0nsoWEmL0JFcf8/MrjWJ0PsbLkov2?= =?us-ascii?Q?f6BCqYAs70lKq77h2mFanztx1IDXLcmxppR/qK+QZ1/CuLjf5vuNGKzURKGa?= =?us-ascii?Q?GbMm/XMuPTW09Uj9hO7cmHE3zAT6d0O1AEg0zyowSBEl5uekZOos9ZUu4kmr?= =?us-ascii?Q?Ps12Hry3Cs5/Z1avnvy1Yvu5qxERkdLM7YdZcX2JSbvMn8FkXaRVBtbuvMES?= =?us-ascii?Q?W83ksOA28+uPqr2c9qcyD8g0i/CWqTzEmnX9FbYxFq3LD9bITHBDTjdHcnFF?= =?us-ascii?Q?8AJPE1GtODcRtbYI67tAZp5uQ4HZ9KBju5gnubZQ10xYGvXUwIcxH9dk6kh2?= =?us-ascii?Q?LCUnazBw3uolKTOTI7Z9RbKIS45h5EdMi4m4xE3ivaOZspbKXnGD8UghGIjl?= =?us-ascii?Q?qyuu5yhV5Jy9DY8/Y3hetb8KdaY+SaqeqMuMxOSrXha6n4OvL1nikX97P1Oj?= =?us-ascii?Q?y5Zd520+LCRfLNRpUhcRURKeioJQlRX1+YhOafFF146CLCVUJYQmKDDQYfTV?= =?us-ascii?Q?3hUZ1/P2enbyk0uAL15EX0r3gGYEZC3Yz9lBN3DnzoerC1ZN02heOzvPJJJm?= =?us-ascii?Q?AOClKj86Q+t7J7I7nG1tmrtghwkKZaAJfhpUl3PE85i+da9r0Q0Pi6XXNc7W?= =?us-ascii?Q?WYF5723zvrf+m007PrZpq5n1Xu4xv69G4pAEHhyYSNoNJXRlBRDgleNMb33U?= =?us-ascii?Q?IQ23AbiYIzr7KG6caAXB7xYJ9Gl2U7hgrFSoN4FofCdnRKnDE2EULGyT9BBn?= =?us-ascii?Q?/wpT+czb5qdY6s2udQBXJzIciFOy4ZKeAvXBs+PU4ttjQ8G399/GX4AoYQN8?= =?us-ascii?Q?9C/LMj7KMUpz9pBGhJZOLVhb47w+BXg0mgNgqG1nePdo+oaIpECySA4RQTTL?= =?us-ascii?Q?a2dnqS13TGIBiPlHhRlFRTWPIwEig5SJbZsAND3zetQzaS+C6+xsR5zZlgHk?= =?us-ascii?Q?q9Dnjcfl05dLTT28SDvzWBvnmKiP/YffNEk+dM91HtBQH+uoxp0q5r1JlIfT?= =?us-ascii?Q?9Qgzle4clQTwb8YxUYG+141r25Uv5JBF6z5rW+BMtxLhKiGoIquMoyUM5sMV?= =?us-ascii?Q?Pv6hZolNt7+7viARFxhpu3Ht0mb06pEuDD8Gm7OFSOHcw4yI8nh7YhmfNzkx?= =?us-ascii?Q?i0DFRJLFlcycrEvxLd1zI7U70YdfdL1FhdHeX/zp14xyQQkHenEFQu0TmSNB?= =?us-ascii?Q?9Nuv2r76H32691w3i85+jWTZmU+G6PUkq62O824KwGSVK5dC1Gc64c0dAKoe?= =?us-ascii?Q?L/a9CaB6c0CZCp4fAKOT8Q66MZrgrc4veZR1L5cstotWZhn61fDreCP0ZSGp?= =?us-ascii?Q?0Q7KbhOh3PqbbAfVqhvxyRTdFYIiaDYqEAWwewrLg24xvGJg2ZO8kFjRAIqS?= =?us-ascii?Q?C2xydw1rgDZqtVxXNJHv2jiIMf70ukAAdbZNSKabDf53xKGTzYcPpVhQpQhN?= =?us-ascii?Q?r1iHEpsLtbxCwZ7cvLc9emha8Lwfd3lfBgML?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jul 2025 10:39:06.6978 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4150f4cc-5c63-4407-b6c1-08ddba1dd643 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026369.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6615 Make the error interrupt enable and error status fields as per SoC. Both these fields can change for different SoC's. Moving them to per SoC data helps to set or clear the required bits only for a SoC. Signed-off-by: Sumit Gupta --- drivers/soc/tegra/cbb/tegra234-cbb.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c index 5d04ed3b2d50d..6116221f0ca61 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -102,6 +102,8 @@ struct tegra234_cbb_fabric { const int max_errors; const struct tegra234_target_lookup *target_map; const int max_targets; + const u32 err_intr_enbl; + const u32 err_status_clr; }; struct tegra234_cbb { @@ -177,7 +179,7 @@ static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb) void __iomem *addr; addr = priv->regs + priv->fabric->notifier_offset; - writel(0x1ff, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0); + writel(priv->fabric->err_intr_enbl, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0); dsb(sy); } @@ -187,7 +189,7 @@ static void tegra234_cbb_error_clear(struct tegra_cbb *cbb) writel(0, priv->mon + FABRIC_MN_INITIATOR_ERR_FORCE_0); - writel(0x3f, priv->mon + FABRIC_MN_INITIATOR_ERR_STATUS_0); + writel(priv->fabric->err_status_clr, priv->mon + FABRIC_MN_INITIATOR_ERR_STATUS_0); dsb(sy); } @@ -709,6 +711,8 @@ static const struct tegra234_cbb_fabric tegra234_aon_fabric = { .max_targets = ARRAY_SIZE(tegra234_aon_target_map), .errors = tegra234_cbb_errors, .max_errors = ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl = 0x7, + .err_status_clr = 0x3f, .notifier_offset = 0x17000, .firewall_base = 0x30000, .firewall_ctl = 0x8d0, @@ -730,6 +734,8 @@ static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = { .max_targets = ARRAY_SIZE(tegra234_bpmp_target_map), .errors = tegra234_cbb_errors, .max_errors = ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl = 0xf, + .err_status_clr = 0x3f, .notifier_offset = 0x19000, .firewall_base = 0x30000, .firewall_ctl = 0x8f0, @@ -807,6 +813,8 @@ static const struct tegra234_cbb_fabric tegra234_cbb_fabric = { .max_targets = ARRAY_SIZE(tegra234_cbb_target_map), .errors = tegra234_cbb_errors, .max_errors = ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl = 0x7f, + .err_status_clr = 0x3f, .notifier_offset = 0x60000, .off_mask_erd = 0x3a004, .firewall_base = 0x10000, @@ -830,6 +838,8 @@ static const struct tegra234_cbb_fabric tegra234_dce_fabric = { .max_targets = ARRAY_SIZE(tegra234_common_target_map), .errors = tegra234_cbb_errors, .max_errors = ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl = 0xf, + .err_status_clr = 0x3f, .notifier_offset = 0x19000, .firewall_base = 0x30000, .firewall_ctl = 0x290, @@ -843,6 +853,8 @@ static const struct tegra234_cbb_fabric tegra234_rce_fabric = { .max_targets = ARRAY_SIZE(tegra234_common_target_map), .errors = tegra234_cbb_errors, .max_errors = ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl = 0xf, + .err_status_clr = 0x3f, .notifier_offset = 0x19000, .firewall_base = 0x30000, .firewall_ctl = 0x290, @@ -856,6 +868,8 @@ static const struct tegra234_cbb_fabric tegra234_sce_fabric = { .max_targets = ARRAY_SIZE(tegra234_common_target_map), .errors = tegra234_cbb_errors, .max_errors = ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl = 0xf, + .err_status_clr = 0x3f, .notifier_offset = 0x19000, .firewall_base = 0x30000, .firewall_ctl = 0x290, @@ -1040,6 +1054,8 @@ static const struct tegra234_cbb_fabric tegra241_cbb_fabric = { .max_targets = ARRAY_SIZE(tegra241_cbb_target_map), .errors = tegra241_cbb_errors, .max_errors = ARRAY_SIZE(tegra241_cbb_errors), + .err_intr_enbl = 0x7, + .err_status_clr = 0x1ff007f, .notifier_offset = 0x60000, .off_mask_erd = 0x40004, .firewall_base = 0x20000, @@ -1065,6 +1081,8 @@ static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = { .max_targets = ARRAY_SIZE(tegra241_bpmp_target_map), .errors = tegra241_cbb_errors, .max_errors = ARRAY_SIZE(tegra241_cbb_errors), + .err_intr_enbl = 0xf, + .err_status_clr = 0x1ff007f, .notifier_offset = 0x19000, .firewall_base = 0x30000, .firewall_ctl = 0x8f0, -- 2.34.1