[PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[Jim Quinlan]

This series enables a new SoC to run with the existing Brcm STB PCIe
driver.  Previous chips all required that an inbound window have a size
that is a power of two; this chip, and next generations chips like it, can
have windows of any reasonable size.

Note: This series must follow the commits of two previous and pending
      series [1,2].

[1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
[2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/

Jim Quinlan (3):
  dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC
  PCI: brcmstb: Acommodate newer SOCs with next-gen PCIe inbound mapping
  PCI: brcmstb: Add 74110a0 SoC configuration details

 .../bindings/pci/brcm,stb-pcie.yaml           |  1 +
 drivers/pci/controller/pcie-brcmstb.c         | 80 ++++++++++++++++++-
 2 files changed, 80 insertions(+), 1 deletion(-)


base-commit: 17bbde2e1716e2ee4b997d476b48ae85c5a47671
prerequisite-patch-id: 82aa80f7ebaa1ee1d48b59bd7f1eb6b21db3c41d
prerequisite-patch-id: e7b6b6e618ee225c9f4892a6078e7b3c4f8b1c73
prerequisite-patch-id: 66cabe0efb02132ce7cf8a849b5bb7f19ab407a2
prerequisite-patch-id: 118fda1b363bc18ef0736f917d1dd5497699156e
prerequisite-patch-id: a48573e6eca090a032c0932ff89f26eae4162db8
-- 
2.34.1

[PATCH 1/3] dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC

[Jim Quinlan]

Adds BCM74110, a Broadcom SetTop box ARM64 based SoC.  Its
inbound window may be set to any size, unlike previous STB
SoCs whose inbound window size must be a power of two.

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
---
 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 5a7b0ed9464d..36bebc290b42 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -27,6 +27,7 @@ properties:
           - brcm,bcm7445-pcie # Broadcom 7445 Arm
           - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5
           - brcm,bcm33940-pcie # Broadcom DOCSIS 4.0 CM w/ 64b ARM
+          - brcm,bcm74110-pcie # Broadcom STB, Arm64
 
   reg:
     maxItems: 1
-- 
2.34.1

Re: [PATCH 1/3] dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC

[Florian Fainelli]

On 7/3/2025 2:53 PM, Jim Quinlan wrote:
> Adds BCM74110, a Broadcom SetTop box ARM64 based SoC.  Its
> inbound window may be set to any size, unlike previous STB
> SoCs whose inbound window size must be a power of two.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-- 
Florian

Re: [PATCH 1/3] dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC

[Rob Herring (Arm)]

On Thu, 03 Jul 2025 17:53:11 -0400, Jim Quinlan wrote:
> Adds BCM74110, a Broadcom SetTop box ARM64 based SoC.  Its
> inbound window may be set to any size, unlike previous STB
> SoCs whose inbound window size must be a power of two.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> ---
>  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[Manivannan Sadhasivam]

On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote:
> This series enables a new SoC to run with the existing Brcm STB PCIe
> driver.  Previous chips all required that an inbound window have a size
> that is a power of two; this chip, and next generations chips like it, can
> have windows of any reasonable size.
> 
> Note: This series must follow the commits of two previous and pending
>       series [1,2].
> 
> [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
> [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/

Have you considered my comment on this series?
https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 1682 bytes --]

On Tue, Aug 19, 2025 at 10:51 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote:
> > This series enables a new SoC to run with the existing Brcm STB PCIe
> > driver.  Previous chips all required that an inbound window have a size
> > that is a power of two; this chip, and next generations chips like it, can
> > have windows of any reasonable size.
> >
> > Note: This series must follow the commits of two previous and pending
> >       series [1,2].
> >
> > [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
> > [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/
>
> Have you considered my comment on this series?
> https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/

Hi Mani,
I'm sorry, I thought I replied to this but obviously I did not.

Your points are valid.  Our PCIe HW block keeps on mutating, and each
time it does we add new code that is triggered off of the soc_base
config setting.  The end result is not easy on the eyes.

I  also have submitted the series "PCI: brcmstb: Include cable-modem
SoCs".  I don't think it has review comments yet, but I am guessing
that you will make the same points.

So it looks like what you are asking for is a refactoring of the
driver and, AFAICT, I need to first submit separate series that does
this before submitting the this and the cable modem submission.  Do
you agree with that?

Regards,
Jim Quinlan
Broadcom STB/CM


>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்

[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4197 bytes --]

Re: [PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[Manivannan Sadhasivam]

On Wed, Aug 20, 2025 at 01:08:41PM GMT, Jim Quinlan wrote:
> On Tue, Aug 19, 2025 at 10:51 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote:
> > > This series enables a new SoC to run with the existing Brcm STB PCIe
> > > driver.  Previous chips all required that an inbound window have a size
> > > that is a power of two; this chip, and next generations chips like it, can
> > > have windows of any reasonable size.
> > >
> > > Note: This series must follow the commits of two previous and pending
> > >       series [1,2].
> > >
> > > [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
> > > [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/
> >
> > Have you considered my comment on this series?
> > https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/
> 
> Hi Mani,
> I'm sorry, I thought I replied to this but obviously I did not.
> 

No issues!

> Your points are valid.  Our PCIe HW block keeps on mutating, and each
> time it does we add new code that is triggered off of the soc_base
> config setting.  The end result is not easy on the eyes.
> 
> I  also have submitted the series "PCI: brcmstb: Include cable-modem
> SoCs".  I don't think it has review comments yet, but I am guessing
> that you will make the same points.
> 

Yes. I intentionally didn't give any comments or merge it since I have the same
refactoring comments.

> So it looks like what you are asking for is a refactoring of the
> driver and, AFAICT, I need to first submit separate series that does
> this before submitting the this and the cable modem submission.  Do
> you agree with that?
> 

Yes, I agree. Refactoring will make life easier for both you and me :)

- Mani

-- 
மணிவண்ணன் சதாசிவம்