From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C928A262A6; Fri, 4 Jul 2025 22:46:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751669220; cv=none; b=Hu5x5Zpce+voI4udPAH0WO8nZdyyPW+7teIgeSj3meCUfhf3SP55IslRGpTX5UHdIAZOgY4tZJghbwaGFTmexZrLcJohIRHgNhFPOLzen+QHX9zHVUkla4BuKZbbjr8EI99WfvaKxUVjyIcRrJ6TclEG7ivvx2NP1nS3UPc34go= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751669220; c=relaxed/simple; bh=WY5tM4XqDysre5wQoyvPEvF7BiLnwxlb/IRaY8GroME=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BKq1eU7jcgYOEtiK7ex+q4JQDFRVvCH/CX28xuYhddxNjtvzfMC4EBSSmdY0vJXLIfQIUPzYlH0qcB2KYe6osMU+IUXf1Xlbt8C4qu5hPRMq4QN+SCn7AZx94RcuaxmrahPZxuog7FoV85cTschwle/nB2GX0xenLL/1B/wO4P8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89F50153B; Fri, 4 Jul 2025 15:46:44 -0700 (PDT) Received: from minigeek.lan (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C72793F63F; Fri, 4 Jul 2025 15:46:55 -0700 (PDT) Date: Fri, 4 Jul 2025 23:45:28 +0100 From: Andre Przywara To: Paul Kocialkowski Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij Subject: Re: [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII Message-ID: <20250704234528.4936fa72@minigeek.lan> In-Reply-To: <20250626080923.632789-3-paulk@sys-base.io> References: <20250626080923.632789-1-paulk@sys-base.io> <20250626080923.632789-3-paulk@sys-base.io> Organization: Arm Ltd. X-Mailer: Claws Mail 4.2.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 26 Jun 2025 10:09:20 +0200 Paul Kocialkowski wrote: Hi, > The Allwinner A100/A133 supports both RGMII and RMII for its Ethernet > MAC (EMAC) controller. Add corresponding pin definitions. Apart from suffixing everything with "0" ("rgmii0_pins: rgmii0-pins"), this matches exactly what I gathered from manual and tested in my own version of this patch a few weeks ago, so with the 0 suffix attached: Reviewed-by: Andre Przywara Cheers, Andre > > Signed-off-by: Paul Kocialkowski > --- > arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi > index bd366389b238..1c4e71b32911 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi > @@ -236,6 +236,21 @@ mmc2_pins: mmc2-pins { > bias-pull-up; > }; > > + rgmii_pins: rgmii-pins { > + pins = "PH0", "PH1", "PH2", "PH3", "PH4", > + "PH5", "PH6", "PH7", "PH9", "PH10", > + "PH14", "PH15", "PH16", "PH17", "PH18"; > + function = "emac"; > + drive-strength = <40>; > + }; > + > + rmii_pins: rmii-pins { > + pins = "PH0", "PH1", "PH2", "PH3", "PH4", > + "PH5", "PH6", "PH7", "PH9", "PH10"; > + function = "emac"; > + drive-strength = <40>; > + }; > + > uart0_pb_pins: uart0-pb-pins { > pins = "PB9", "PB10"; > function = "uart0";