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* [PATCH v2 0/3] arm64: dts: add descriptions for solidrun i.mx8mp based boards
@ 2025-07-07 16:11 Josua Mayer
  2025-07-07 16:11 ` [PATCH v2 1/3] dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards Josua Mayer
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Josua Mayer @ 2025-07-07 16:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: Yazan Shhady, Mikhail Anikin, Jon Nettleton, devicetree,
	linux-kernel, imx, linux-arm-kernel, Josua Mayer

Add bindings and descriptions for the SolidRun i.MX8M Plus based System
on Module and various reference boards based on said module:

- CuBox-M
- HummingBoard Mate
- HummingBoard Pro
- HummingBoard Pulse
- HummingBoard Ripple

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Changes in v2:
- Removed invalid spidev (rohm,dh2228fv) node for mikrobus header spi
  (Reported-by: Krzysztof Kozlowski <krzk@kernel.org>)
- Added Acked-by: Rob Herring (Arm) <robh@kernel.org> on bindings
- Added m.2 connector reset hog for hummingboard pulse (usb-3.0 only,
  pulled low from u-boot)
- Link to v1: https://lore.kernel.org/r/20250614-imx8mp-sr-som-v1-0-3ca3269883c4@solid-run.com

---
Josua Mayer (3):
      dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards
      arm64: dts: add description for solidrun imx8mp som and cubox-m
      arm64: dts: add description for solidrun imx8mp hummingboard variants

 Documentation/devicetree/bindings/arm/fsl.yaml     |  11 +
 arch/arm64/boot/dts/freescale/Makefile             |   5 +
 arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts   | 224 ++++++++
 .../dts/freescale/imx8mp-hummingboard-mate.dts     |  31 ++
 .../boot/dts/freescale/imx8mp-hummingboard-pro.dts |  76 +++
 .../freescale/imx8mp-hummingboard-pulse-codec.dtsi |  59 ++
 .../imx8mp-hummingboard-pulse-common.dtsi          | 384 +++++++++++++
 .../freescale/imx8mp-hummingboard-pulse-hdmi.dtsi  |  44 ++
 .../freescale/imx8mp-hummingboard-pulse-m2con.dtsi |  60 +++
 .../imx8mp-hummingboard-pulse-mini-hdmi.dtsi       |  81 +++
 .../dts/freescale/imx8mp-hummingboard-pulse.dts    |  84 +++
 .../dts/freescale/imx8mp-hummingboard-ripple.dts   |  31 ++
 arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi   | 591 +++++++++++++++++++++
 13 files changed, 1681 insertions(+)
---
base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
change-id: 20250614-imx8mp-sr-som-ceef5bef1bed

Best regards,
-- 
Josua Mayer <josua@solid-run.com>


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH v2 1/3] dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards
  2025-07-07 16:11 [PATCH v2 0/3] arm64: dts: add descriptions for solidrun i.mx8mp based boards Josua Mayer
@ 2025-07-07 16:11 ` Josua Mayer
  2025-07-07 16:11 ` [PATCH v2 2/3] arm64: dts: add description for solidrun imx8mp som and cubox-m Josua Mayer
  2025-07-07 16:11 ` [PATCH v2 3/3] arm64: dts: add description for solidrun imx8mp hummingboard variants Josua Mayer
  2 siblings, 0 replies; 7+ messages in thread
From: Josua Mayer @ 2025-07-07 16:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: Yazan Shhady, Mikhail Anikin, Jon Nettleton, devicetree,
	linux-kernel, imx, linux-arm-kernel, Josua Mayer

Add bindings for SolidRun i.MX8M Plus System on Module based boards:

- CuBox-M is a complete produc with enclosure including the SoM
- HummingBoard Mate/Pro/Pulse/Ripple are evaluation boards with common
  design but different available interfaces.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index d3b5e6923e4166e35760c17c772aa0195137de93..1462023f35b7be47a5cb855fa64025d07361d550 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1189,6 +1189,17 @@ properties:
           - const: polyhex,imx8mp-debix-som-a       # Polyhex Debix SOM A
           - const: fsl,imx8mp
 
+      - description: SolidRun i.MX8MP SoM based boards
+        items:
+          - enum:
+              - solidrun,imx8mp-cubox-m             # SolidRun i.MX8MP SoM on CuBox-M
+              - solidrun,imx8mp-hummingboard-mate   # SolidRun i.MX8MP SoM on HummingBoard Mate
+              - solidrun,imx8mp-hummingboard-pro    # SolidRun i.MX8MP SoM on HummingBoard Pro
+              - solidrun,imx8mp-hummingboard-pulse  # SolidRun i.MX8MP SoM on HummingBoard Pulse
+              - solidrun,imx8mp-hummingboard-ripple # SolidRun i.MX8MP SoM on HummingBoard Ripple
+          - const: solidrun,imx8mp-sr-som
+          - const: fsl,imx8mp
+
       - description: Toradex Boards with SMARC iMX8M Plus Modules
         items:
           - const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board

-- 
2.43.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH v2 2/3] arm64: dts: add description for solidrun imx8mp som and cubox-m
  2025-07-07 16:11 [PATCH v2 0/3] arm64: dts: add descriptions for solidrun i.mx8mp based boards Josua Mayer
  2025-07-07 16:11 ` [PATCH v2 1/3] dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards Josua Mayer
@ 2025-07-07 16:11 ` Josua Mayer
  2025-07-11  7:49   ` Shawn Guo
  2025-07-07 16:11 ` [PATCH v2 3/3] arm64: dts: add description for solidrun imx8mp hummingboard variants Josua Mayer
  2 siblings, 1 reply; 7+ messages in thread
From: Josua Mayer @ 2025-07-07 16:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: Yazan Shhady, Mikhail Anikin, Jon Nettleton, devicetree,
	linux-kernel, imx, linux-arm-kernel, Josua Mayer

Add description for the SolidRun i.MX8M Plus based System on Module, and
the CuBox-M.

The SoM features:
- 2x 1Gbps Ethernet with PHY
- eMMC
- 1/2/3/8GB DDR
- MIPI-CSI Camera Connector (not described without specific camera)

The CuBox-M is a complete product with enclosure featuring:
- 1x 1Gbps RJ45 Ethernet Port
- 2x USB-3.0 Type A
- HDMI connector
- microSD connector
- microUSB connector for console (using fdtdi chip)
- IR receiver
- RTC with backup battery

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 arch/arm64/boot/dts/freescale/Makefile           |   1 +
 arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts | 224 +++++++++
 arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 591 +++++++++++++++++++++++
 3 files changed, 816 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 0b473a23d12008ff79d6467d9e1c7ab2c4d6a9a6..e98c15eb949957a193eb3a7612f3f0f2b04790af 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -194,6 +194,7 @@ imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
new file mode 100644
index 0000000000000000000000000000000000000000..13da5e0196a3fc168efdde63d86f0fe776f999fb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+
+#include "imx8mp-sr-som.dtsi"
+
+/ {
+	model = "SolidRun i.MX8MP CuBox-M";
+	compatible = "solidrun,imx8mp-cubox-m",
+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		/delete-property/ ethernet1;
+		rtc0 = &carrier_rtc;
+		rtc1 = &snvs_rtc;
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_pins>;
+		linux,autosuspend-period = <125>;
+		wakeup-source;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins>;
+
+		status {
+			label = "status";
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_HEARTBEAT;
+		};
+	};
+
+	sound-hdmi {
+		compatible = "fsl,imx-audio-hdmi";
+		model = "audio-hdmi";
+		audio-cpu = <&aud2htx>;
+		hdmi-out;
+		status = "okay";
+	};
+
+	vbus: regulator-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vbus_pins>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vmmc: regulator-mmc {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vmmc_pins>;
+		regulator-name = "vmmc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <250>;
+	};
+};
+
+&aud2htx {
+	status = "okay";
+};
+
+&fec {
+	/* this board does not use second phy / ethernet on SoM */
+	status = "disabled";
+};
+
+&hdmi_pvi {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+};
+
+&hdmi_tx_phy {
+	status = "okay";
+};
+
+&i2c3 {
+	carrier_rtc: rtc@32 {
+		compatible = "epson,rx8130";
+		reg = <0x32>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_pins>;
+
+	hdmi_pins: pinctrl-hdmi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
+		>;
+	};
+
+	ir_pins: pinctrl-ir-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x4f
+		>;
+	};
+
+	led_pins: pinctrl-led-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x0
+		>;
+	};
+
+	usdhc2_pins: pinctrl-usdhc2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
+		>;
+	};
+
+	usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
+		>;
+	};
+
+	usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
+		>;
+	};
+
+	vbus_pins: pinctrl-vbus-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x100
+		>;
+	};
+
+	vmmc_pins: pinctrl-vmmc-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x0
+		>;
+	};
+};
+
+&lcdif3 {
+	status = "okay";
+};
+
+&usb3_phy0 {
+	fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
+	vbus-supply = <&vbus>;
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_phy1 {
+	fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
+	vbus-supply = <&vbus>;
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "host";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&usdhc2_pins>;
+	pinctrl-1 = <&usdhc2_100mhz_pins>;
+	pinctrl-2 = <&usdhc2_200mhz_pins>;
+	vmmc-supply = <&vmmc>;
+	bus-width = <4>;
+	cap-power-off-card;
+	full-pwr-cycle;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..a7ee0a4d4f765581dbc27d3c5dfc656b026d27e6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
@@ -0,0 +1,591 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include "imx8mp.dtsi"
+
+/ {
+	model = "SolidRun i.MX8MP SoM";
+	compatible = "solidrun,imx8mp-sr-som", "fsl,imx8mp";
+
+	chosen {
+		bootargs = "earlycon=ec_imx6q,0x30890000,115200";
+		stdout-path = &uart2;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0 0xc0000000>,
+		      <0x1 0x00000000 0 0xc0000000>;
+	};
+
+	usdhc1_pwrseq: usdhc1-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+	};
+
+	v_1_8: regulator-1-8 {
+		compatible = "regulator-fixed";
+		regulator-name = "1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	v_3_3: regulator-3-3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&eqos_pins>, <&phy0_pins>;
+	phy-mode = "rgmii-id";
+	phy = <&phy0>;
+	snps,force_thresh_dma_mode;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+			interrupt-parent = <&gpio4>;
+			interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <5>;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,priority = <0x2>;
+		};
+
+		queue2 {
+			snps,dcb-algorithm;
+			snps,priority = <0x4>;
+		};
+
+		queue3 {
+			snps,dcb-algorithm;
+			snps,priority = <0x8>;
+		};
+
+		queue4 {
+			snps,dcb-algorithm;
+			snps,priority = <0xf0>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <5>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,priority = <0x1>;
+			snps,map-to-dma-channel = <0>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,priority = <0x2>;
+			snps,map-to-dma-channel = <1>;
+		};
+
+		queue2 {
+			snps,dcb-algorithm;
+			snps,priority = <0x4>;
+			snps,map-to-dma-channel = <2>;
+		};
+
+		queue3 {
+			snps,dcb-algorithm;
+			snps,priority = <0x8>;
+			snps,map-to-dma-channel = <3>;
+		};
+
+		queue4 {
+			snps,dcb-algorithm;
+			snps,priority = <0xf0>;
+			snps,map-to-dma-channel = <4>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&fec_pins>, <&phy1_pins>;
+	phy-mode = "rgmii-id";
+	phy = <&phy1>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0x1>;
+			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+			interrupt-parent = <&gpio4>;
+			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-1 = <&i2c1_gpio_pins>;
+	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	som_eeprom: eeprom@50{
+		compatible = "st,24c01", "atmel,24c01";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	pmic: pmic@25 {
+		compatible = "nxp,pca9450c";
+		reg = <0x25>;
+		pinctrl-0 = <&pmic_pins>;
+		pinctrl-names = "default";
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 GPIO_ACTIVE_LOW>;
+		nxp,i2c-lt-enable;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+			};
+
+			buck4: BUCK4{
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5{
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-1 = <&i2c2_gpio_pins>;
+	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&i2c3_pins>;
+	pinctrl-1 = <&i2c3_gpio_pins>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+&i2c4 {
+	/* routed to basler camera connector */
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&i2c4_pins>;
+	pinctrl-1 = <&i2c4_gpio_pins>;
+	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+&iomuxc {
+	eqos_pins: pinctrl-eqos-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+		>;
+	};
+
+	fec_pins: pinctrl-fec-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
+		>;
+	};
+
+	i2c1_pins: pinctrl-i2c1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c3
+		>;
+	};
+
+	i2c1_gpio_pins: pinctrl-i2c1-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c3
+		>;
+	};
+
+	i2c2_pins: pinctrl-i2c2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
+		>;
+	};
+
+	i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c3
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c3
+		>;
+	};
+
+	i2c3_pins: pinctrl-i2c3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
+		>;
+	};
+
+	i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c3
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c3
+		>;
+	};
+
+	i2c4_pins: pinctrl-i2c4-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3
+		>;
+	};
+
+	i2c4_gpio_pins: pinctrl-i2c4-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20			0x400001c3
+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21			0x400001c3
+		>;
+	};
+
+	phy0_pins: pinctrl-phy0-grp {
+		fsl,pins = <
+			/* RESET_N: weak i/o, open drain, external 1k pull-up */
+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x20
+			/* INT_N: weak i/o, open drain, internal pull-up */
+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x160
+		>;
+	};
+
+	phy1_pins: pinctrl-phy-1-grp {
+		fsl,pins = <
+			/* RESET_N: weak i/o, open drain, external 1k pull-up */
+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x20
+			/* INT_N: weak i/o, open drain, internal pull-up */
+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x160
+		>;
+	};
+
+	pmic_pins: pinctrl-pmic-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41
+		>;
+	};
+
+	uart1_pins: pinctrl-uart1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x140
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x140
+			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS		0x140
+			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS		0x140
+			/* BT_REG_ON */
+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x0
+			/* BT_WAKE_DEV */
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x0
+			/* BT_WAKE_HOST */
+			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x100
+		>;
+	};
+
+	uart2_pins: pinctrl-uart2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
+		>;
+	};
+
+	usdhc1_pins: pinctrl-usdhc1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
+			/* WL_REG_ON */
+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x0
+			/* WL_WAKE_HOST */
+			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x100
+		>;
+	};
+
+	usdhc1_100mhz_pins: pinctrl-usdhc1g-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
+		>;
+	};
+
+	usdhc1_200mhz_pins: pinctrl-usdhc1-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
+		>;
+	};
+
+	usdhc3_pins: pinctrl-usdhc3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
+		>;
+	};
+
+	usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
+		>;
+	};
+
+	usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
+		>;
+	};
+
+	wdog1_pins: pinctrl-wdog1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0x140
+		>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	uart-has-rtscts;
+	/* select 80MHz parent clock to support maximum baudrate 4Mbps */
+	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+		/* Murata 1MW module supports max. 3M baud */
+		max-speed = <3000000>;
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usdhc1_pins>;
+	pinctrl-1 = <&usdhc1_100mhz_pins>;
+	pinctrl-2 = <&usdhc1_200mhz_pins>;
+	vmmc-supply = <&v_3_3>;
+	vqmmc-supply = <&v_1_8>;
+	bus-width = <4>;
+	mmc-pwrseq = <&usdhc1_pwrseq>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&usdhc3_pins>;
+	pinctrl-1 = <&usdhc3_100mhz_pins>;
+	pinctrl-2 = <&usdhc3_200mhz_pins>;
+	vmmc-supply = <&v_3_3>;
+	vqmmc-supply = <&v_1_8>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wdog1_pins>;
+	status = "okay";
+};
+
+/*
+ * Reserve all physical memory from within the first 1GB of DDR address
+ * space to avoid panic on low memory systems.
+ */
+&dsp_reserved {
+	reg = <0 0x6f000000 0 0x1000000>;
+};

-- 
2.43.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH v2 3/3] arm64: dts: add description for solidrun imx8mp hummingboard variants
  2025-07-07 16:11 [PATCH v2 0/3] arm64: dts: add descriptions for solidrun i.mx8mp based boards Josua Mayer
  2025-07-07 16:11 ` [PATCH v2 1/3] dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards Josua Mayer
  2025-07-07 16:11 ` [PATCH v2 2/3] arm64: dts: add description for solidrun imx8mp som and cubox-m Josua Mayer
@ 2025-07-07 16:11 ` Josua Mayer
  2025-07-11  8:01   ` Shawn Guo
  2 siblings, 1 reply; 7+ messages in thread
From: Josua Mayer @ 2025-07-07 16:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: Yazan Shhady, Mikhail Anikin, Jon Nettleton, devicetree,
	linux-kernel, imx, linux-arm-kernel, Josua Mayer

Add descriptions for the SolidRun i.MX8M Plus System on Module based
HummingBoard product-line. They share a common designed based on the
"Pulse" version, defined by various assembly options.

The HummingBoard Pulse features:
- 2x RJ45 Ethernet
- 2x USB-3.0 Type A
- HDMI connector
- mini-HDMI connector
- microSD connector
- mini-PCI-E connector with SIM slot supporting USB-2.0/3.0 interfaces
- M.2 connector with SIM slot supporting USB-2.0/3.0 interfaces
- MIPI-CSI Camera Connector (not described without specific camera)
- 3.5mm Analog Stereo Out / Microphone In Headphone Jack
- RTC with backup battery

The variants Mate and Ripple are reduced versions of Pulse.

The HummingBoard Pro extends Pulse with PCI-E on M.2 connector.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 arch/arm64/boot/dts/freescale/Makefile             |   4 +
 .../dts/freescale/imx8mp-hummingboard-mate.dts     |  31 ++
 .../boot/dts/freescale/imx8mp-hummingboard-pro.dts |  76 ++++
 .../freescale/imx8mp-hummingboard-pulse-codec.dtsi |  59 ++++
 .../imx8mp-hummingboard-pulse-common.dtsi          | 384 +++++++++++++++++++++
 .../freescale/imx8mp-hummingboard-pulse-hdmi.dtsi  |  44 +++
 .../freescale/imx8mp-hummingboard-pulse-m2con.dtsi |  60 ++++
 .../imx8mp-hummingboard-pulse-mini-hdmi.dtsi       |  81 +++++
 .../dts/freescale/imx8mp-hummingboard-pulse.dts    |  84 +++++
 .../dts/freescale/imx8mp-hummingboard-ripple.dts   |  31 ++
 10 files changed, 854 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index e98c15eb949957a193eb3a7612f3f0f2b04790af..ccc1d6f98495589cb6a55b198d1933bcf076fcb8 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -203,6 +203,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts
new file mode 100644
index 0000000000000000000000000000000000000000..00614f5d58ea9de51aad9a5f36212dc3d4f3ecaf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mp-sr-som.dtsi"
+#include "imx8mp-hummingboard-pulse-common.dtsi"
+#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
+
+/ {
+	model = "SolidRun i.MX8MP HummingBoard Mate";
+	compatible = "solidrun,imx8mp-hummingboard-mate",
+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		/delete-property/ ethernet1;
+	};
+};
+
+&fec {
+	/* this board does not use second phy / ethernet on SoM */
+	status = "disabled";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts
new file mode 100644
index 0000000000000000000000000000000000000000..36cd452f1583987a1e826d33798d9aecaaf21568
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#include "imx8mp-sr-som.dtsi"
+#include "imx8mp-hummingboard-pulse-codec.dtsi"
+#include "imx8mp-hummingboard-pulse-common.dtsi"
+#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
+#include "imx8mp-hummingboard-pulse-m2con.dtsi"
+#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
+
+/ {
+	model = "SolidRun i.MX8MP HummingBoard Pro";
+	compatible = "solidrun,imx8mp-hummingboard-pro",
+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>,
+		    <&m2_wwan_wake_pins>;
+};
+
+&pcie {
+	pinctrl-0 = <&m2_reset_pins>;
+	pinctrl-names = "default";
+	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie_phy {
+	clocks = <&hsio_blk_ctrl>;
+	clock-names = "ref";
+	fsl,clkreq-unsupported;
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+	status = "okay";
+};
+
+&phy0 {
+	leds {
+		/* ADIN1300 LED_0 pin */
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_ORANGE>;
+			function = LED_FUNCTION_LAN;
+			default-state = "keep";
+		};
+
+		/delete-node/ led@1;
+	};
+};
+
+&phy1 {
+	leds {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* ADIN1300 LED_0 pin */
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			default-state = "keep";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..fd16916676db4ec6f0e66d9c52355c37fe06b971
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/ {
+	sound-wm8904 {
+		compatible = "fsl,imx-audio-wm8904";
+		model = "audio-wm8904";
+		audio-cpu = <&sai3>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"AMIC", "MICBIAS",
+			"IN2R", "AMIC";
+	};
+};
+
+&i2c2 {
+	codec: codec@1a {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;
+		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
+		clock-names = "mclk";
+		AVDD-supply = <&v_1_8>;
+		CPVDD-supply = <&v_1_8>;
+		DBVDD-supply = <&v_3_3>;
+		DCVDD-supply = <&v_1_8>;
+		MICVDD-supply = <&v_3_3>;
+	};
+};
+
+&iomuxc {
+	sai3_pins: pinctrl-sai3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6
+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
+		>;
+	};
+};
+
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sai3_pins>;
+	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <12288000>;
+	clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
+		 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
+		 <&clk IMX8MP_CLK_DUMMY>;
+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..3a43cf3e2ca00741fe15cd834df0ac7c9119ad09
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		rtc0 = &carrier_rtc;
+		rtc1 = &snvs_rtc;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins>;
+
+		led-0 {
+			label = "D30";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		led-1 {
+			label = "D31";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		led-2 {
+			label = "D32";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		led-3 {
+			label = "D33";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		led-4 {
+			label = "D34";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+
+	rfkill-mpcie-wifi {
+		/*
+		 * The mpcie connector only has USB,
+		 * therefore this rfkill is for cellular radios only.
+		 */
+		compatible = "rfkill-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&mpcie_rfkill_pins>;
+		label = "mpcie radio";
+		radio-type = "wwan";
+		/* rfkill-gpio inverts internally */
+		shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+	};
+
+	vmmc: regulator-mmc {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vmmc_pins>;
+		regulator-name = "vmmc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <250>;
+	};
+
+	vbus1: regulator-vbus-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus1";
+		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vbus1_pins>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vbus2: regulator-vbus-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus2";
+		gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vbus2_pins>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	v_1_2: regulator-1-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "1v2";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+	};
+
+	vmpcie {
+		/* supplies mpcie and m2 connectors */
+		compatible = "regulator-fixed";
+		regulator-name = "vmpcie";
+		gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vmpcie_pins>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+};
+
+/* mikrobus spi */
+&ecspi2 {
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mikro_spi_pins>;
+	status = "okay";
+};
+
+&gpio1 {
+	pinctrl-0 = <&mpcie_reset_pins>;
+	pinctrl-names = "default";
+
+	mpcie-reset-hog {
+		gpio-hog;
+		gpios = <1 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "mpcie-reset";
+	};
+};
+
+&i2c3 {
+	carrier_rtc: rtc@69 {
+		compatible = "abracon,ab1805";
+		reg = <0x69>;
+		abracon,tc-diode = "schottky";
+		abracon,tc-resistor = <3>;
+	};
+
+	carrier_eeprom: eeprom@57{
+		compatible = "st,24c02", "atmel,24c02";
+		reg = <0x57>;
+		pagesize = <16>;
+	};
+};
+
+&iomuxc {
+	csi_pins: pinctrl-csi-grp {
+		fsl,pins = <
+			/* Pin 24: STROBE */
+			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07		0x0
+		>;
+	};
+
+	mikro_int_pins: pinctrl-mikro-int-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x0
+		>;
+	};
+
+	mikro_pwm_pins: pinctrl-mikro-pwm-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08		0x0
+		>;
+	};
+
+	mikro_rst_pins: pinctrl-mikro-rst-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x0
+		>;
+	};
+
+	mikro_spi_pins: pinctrl-mikro-spi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0		0x40000
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
+		>;
+	};
+
+	mikro_uart_pins: pinctrl-mikro-uart-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
+			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
+		>;
+	};
+
+	led_pins: pinctrl-led-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x0
+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x0
+			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23		0x0
+			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24		0x0
+			MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28		0x0
+		>;
+	};
+
+	mpcie_reset_pins: pinctrl-mpcie-reset-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x0
+		>;
+	};
+
+	mpcie_rfkill_pins: pinctrl-pcie-rfkill-grp {
+		fsl,pins = <
+			/* weak i/o, open drain */
+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x20
+		>;
+	};
+
+	usb_hub_pins: pinctrl-usb-hub-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x0
+		>;
+	};
+
+	usdhc2_pins: pinctrl-usdhc2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
+		>;
+	};
+
+	usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
+		>;
+	};
+
+	usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
+			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
+		>;
+	};
+
+	vbus1_pins: pinctrl-vbus-1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x20
+		>;
+	};
+
+	vbus2_pins: pinctrl-vbus-2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x20
+		>;
+	};
+
+	vmmc_pins: pinctrl-vmmc-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41
+		>;
+	};
+
+	vmpcie_pins: pinctrl-vmpcie-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x0
+		>;
+	};
+};
+
+&phy0 {
+	leds {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* ADIN1300 LED_0 pin */
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_ORANGE>;
+			function = LED_FUNCTION_LAN;
+			default-state = "keep";
+		};
+
+		/* ADIN1300 LINK_ST pin */
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			default-state = "keep";
+		};
+	};
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+/* mikrobus uart */
+&uart3 {
+	status = "okay";
+};
+
+&usb3_phy0 {
+	fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
+	vbus-supply = <&vbus2>;
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_phy1 {
+	vbus-supply = <&vbus1>;
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "host";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb_hub_pins>;
+
+	hub_2_0: hub@1 {
+		compatible = "usb4b4,6502", "usb4b4,6506";
+		reg = <1>;
+		peer-hub = <&hub_3_0>;
+		reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+		vdd-supply = <&v_1_2>;
+		vdd2-supply = <&v_3_3>;
+	};
+
+	hub_3_0: hub@2 {
+		compatible = "usb4b4,6500", "usb4b4,6504";
+		reg = <2>;
+		peer-hub = <&hub_2_0>;
+		reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+		vdd-supply = <&v_1_2>;
+		vdd2-supply = <&v_3_3>;
+	};
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&usdhc2_pins>;
+	pinctrl-1 = <&usdhc2_100mhz_pins>;
+	pinctrl-2 = <&usdhc2_200mhz_pins>;
+	vmmc-supply = <&vmmc>;
+	bus-width = <4>;
+	cap-power-off-card;
+	full-pwr-cycle;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..d7a999c0d7e06a8c47a61632a59eb97faea9e3d4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/ {
+	sound-hdmi {
+		compatible = "fsl,imx-audio-hdmi";
+		model = "audio-hdmi";
+		audio-cpu = <&aud2htx>;
+		hdmi-out;
+	};
+};
+
+&aud2htx {
+	status = "okay";
+};
+
+&hdmi_pvi {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+};
+
+&hdmi_tx_phy {
+	status = "okay";
+};
+
+&iomuxc {
+	hdmi_pins: pinctrl-hdmi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
+		>;
+	};
+};
+
+&lcdif3 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..b879ca4ed21428b8d4c6866f9a827bcfbef1caee
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/ {
+	rfkill-m2-gnss {
+		compatible = "rfkill-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&m2_gnss_rfkill_pins>;
+		label = "m.2 GNSS";
+		radio-type = "gps";
+		/* rfkill-gpio inverts internally */
+		shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+	};
+
+	/* M.2 is B-keyed, so w-disable is for WWAN */
+	rfkill-m2-wwan {
+		compatible = "rfkill-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&m2_wwan_rfkill_pins>;
+		label = "m.2 WWAN";
+		radio-type = "wwan";
+		/* rfkill-gpio inverts internally */
+		shutdown-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&iomuxc {
+	m2_gnss_rfkill_pins: pinctrl-m2-gnss-rfkill-grp {
+		fsl,pins = <
+			/* weak i/o, open drain */
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x20
+		>;
+	};
+
+	m2_wwan_rfkill_pins: pinctrl-m2-wwan-rfkill-grp {
+		fsl,pins = <
+			/* weak i/o, open drain */
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x20
+		>;
+	};
+
+	m2_wwan_wake_pins: pinctrl-m2-wwan-wake-grp {
+		fsl,pins = <
+			/* weak i/o, open drain */
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x20
+		>;
+	};
+
+	m2_reset_pins: pinctrl-m2-reset-grp {
+		fsl,pins = <
+			/*
+			 * 3.3V domain on SoC, set open-drain to ensure
+			 * 1.8V logic on connector
+			 */
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x20
+		>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..46916ddc053355b6708629898fa13e55c6493cc2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/ {
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+		type = "c";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&adv7535_out>;
+			};
+		};
+	};
+};
+
+&i2c3 {
+	hdmi@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>, <0x3f>, <0x3c>, <0x38>;
+		reg-names = "main", "edid", "cec", "packet";
+		adi,dsi-lanes = <4>;
+		avdd-supply = <&v_1_8>;
+		dvdd-supply = <&v_1_8>;
+		pvdd-supply = <&v_1_8>;
+		a2vdd-supply = <&v_1_8>;
+		v3p3-supply = <&v_3_3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mini_hdmi_pins>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				adv7535_from_dsim: endpoint {
+					remote-endpoint = <&dsim_to_adv7535>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				adv7535_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
+		};
+	};
+};
+
+&iomuxc {
+	mini_hdmi_pins: pinctrl-mini-hdmi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x0
+		>;
+	};
+};
+
+&lcdif1 {
+	status = "okay";
+};
+
+&mipi_dsi {
+	samsung,esc-clock-frequency = <10000000>;
+	status = "okay";
+
+	port@1 {
+		dsim_to_adv7535: endpoint {
+			remote-endpoint = <&adv7535_from_dsim>;
+			attach-bridge;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts
new file mode 100644
index 0000000000000000000000000000000000000000..e0d6f281837f106bb0b4661d8fe54eaa2cafc3c2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#include "imx8mp-sr-som.dtsi"
+#include "imx8mp-hummingboard-pulse-codec.dtsi"
+#include "imx8mp-hummingboard-pulse-common.dtsi"
+#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
+#include "imx8mp-hummingboard-pulse-m2con.dtsi"
+#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
+
+/ {
+	model = "SolidRun i.MX8MP HummingBoard Pulse";
+	compatible = "solidrun,imx8mp-hummingboard-pulse",
+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &pcie_eth;
+	};
+};
+
+&fec {
+	/* this board does not use second phy / ethernet on SoM */
+	status = "disabled";
+};
+
+&gpio1 {
+	pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>;
+	pinctrl-names = "default";
+
+	m2-reset-hog {
+		gpio-hog;
+		gpios = <6 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "m2-reset";
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>,
+		    <&m2_wwan_wake_pins>;
+
+	pcie_eth_pins: pinctrl-pcie-eth-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x0
+		>;
+	};
+};
+
+&pcie {
+	pinctrl-0 = <&pcie_eth_pins>;
+	pinctrl-names = "default";
+	reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	root@0,0 {
+		compatible = "pci16c3,abcd";
+		reg = <0x00000000 0 0 0 0>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		/* Intel i210 */
+		pcie_eth: ethernet@1,0 {
+			compatible = "pci8086,157b";
+			reg = <0x00010000 0 0 0 0>;
+		};
+	};
+};
+
+&pcie_phy {
+	clocks = <&hsio_blk_ctrl>;
+	clock-names = "ref";
+	fsl,clkreq-unsupported;
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts
new file mode 100644
index 0000000000000000000000000000000000000000..4ce5b799b6abc514ca00e2e2134d5ff1606dc87d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mp-sr-som.dtsi"
+#include "imx8mp-hummingboard-pulse-common.dtsi"
+#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
+
+/ {
+	model = "SolidRun i.MX8MP HummingBoard Ripple";
+	compatible = "solidrun,imx8mp-hummingboard-ripple",
+		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		/delete-property/ ethernet1;
+	};
+};
+
+&fec {
+	/* this board does not use second phy / ethernet on SoM */
+	status = "disabled";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>;
+};

-- 
2.43.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: add description for solidrun imx8mp som and cubox-m
  2025-07-07 16:11 ` [PATCH v2 2/3] arm64: dts: add description for solidrun imx8mp som and cubox-m Josua Mayer
@ 2025-07-11  7:49   ` Shawn Guo
  2025-07-13 11:15     ` Josua Mayer
  0 siblings, 1 reply; 7+ messages in thread
From: Shawn Guo @ 2025-07-11  7:49 UTC (permalink / raw)
  To: Josua Mayer
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	Yazan Shhady, Mikhail Anikin, Jon Nettleton, devicetree,
	linux-kernel, imx, linux-arm-kernel

On Mon, Jul 07, 2025 at 07:11:57PM +0300, Josua Mayer wrote:
> Add description for the SolidRun i.MX8M Plus based System on Module, and
> the CuBox-M.
> 
> The SoM features:
> - 2x 1Gbps Ethernet with PHY
> - eMMC
> - 1/2/3/8GB DDR
> - MIPI-CSI Camera Connector (not described without specific camera)
> 
> The CuBox-M is a complete product with enclosure featuring:
> - 1x 1Gbps RJ45 Ethernet Port
> - 2x USB-3.0 Type A
> - HDMI connector
> - microSD connector
> - microUSB connector for console (using fdtdi chip)
> - IR receiver
> - RTC with backup battery
> 
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
>  arch/arm64/boot/dts/freescale/Makefile           |   1 +
>  arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts | 224 +++++++++
>  arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 591 +++++++++++++++++++++++
>  3 files changed, 816 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 0b473a23d12008ff79d6467d9e1c7ab2c4d6a9a6..e98c15eb949957a193eb3a7612f3f0f2b04790af 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -194,6 +194,7 @@ imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..13da5e0196a3fc168efdde63d86f0fe776f999fb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
> @@ -0,0 +1,224 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +
> +#include "imx8mp-sr-som.dtsi"
> +
> +/ {
> +	model = "SolidRun i.MX8MP CuBox-M";
> +	compatible = "solidrun,imx8mp-cubox-m",
> +		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
> +
> +	aliases {
> +		ethernet0 = &eqos;
> +		/delete-property/ ethernet1;
> +		rtc0 = &carrier_rtc;
> +		rtc1 = &snvs_rtc;
> +	};
> +
> +	ir-receiver {
> +		compatible = "gpio-ir-receiver";
> +		gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&ir_pins>;
> +		linux,autosuspend-period = <125>;
> +		wakeup-source;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&led_pins>;
> +
> +		status {
> +			label = "status";
> +			color = <LED_COLOR_ID_RED>;
> +			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
> +			function = LED_FUNCTION_HEARTBEAT;
> +		};
> +	};
> +
> +	sound-hdmi {
> +		compatible = "fsl,imx-audio-hdmi";
> +		model = "audio-hdmi";
> +		audio-cpu = <&aud2htx>;
> +		hdmi-out;
> +		status = "okay";

We usually use "okay" to flip a "disabled" device.  It's not required
here I guess?

> +	};
> +
> +	vbus: regulator-vbus {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vbus";
> +		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vbus_pins>;
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +	};
> +
> +	vmmc: regulator-mmc {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vmmc_pins>;
> +		regulator-name = "vmmc";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> +		startup-delay-us = <250>;
> +	};
> +};
> +
> +&aud2htx {
> +	status = "okay";
> +};
> +
> +&fec {
> +	/* this board does not use second phy / ethernet on SoM */
> +	status = "disabled";
> +};
> +
> +&hdmi_pvi {
> +	status = "okay";
> +};
> +
> +&hdmi_tx {
> +	status = "okay";
> +};
> +
> +&hdmi_tx_phy {
> +	status = "okay";
> +};
> +
> +&i2c3 {
> +	carrier_rtc: rtc@32 {
> +		compatible = "epson,rx8130";
> +		reg = <0x32>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&hdmi_pins>;
> +
> +	hdmi_pins: pinctrl-hdmi-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
> +			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
> +			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
> +			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
> +		>;
> +	};
> +
> +	ir_pins: pinctrl-ir-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x4f
> +		>;
> +	};
> +
> +	led_pins: pinctrl-led-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x0
> +		>;
> +	};
> +
> +	usdhc2_pins: pinctrl-usdhc2-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
> +		>;
> +	};
> +
> +	usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
> +		>;
> +	};
> +
> +	usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
> +		>;
> +	};
> +
> +	vbus_pins: pinctrl-vbus-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x100
> +		>;
> +	};
> +
> +	vmmc_pins: pinctrl-vmmc-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x0
> +		>;
> +	};
> +};
> +
> +&lcdif3 {
> +	status = "okay";
> +};
> +
> +&usb3_phy0 {
> +	fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
> +	vbus-supply = <&vbus>;
> +	status = "okay";
> +};
> +
> +&usb3_0 {
> +	status = "okay";
> +};
> +
> +&usb3_phy1 {
> +	fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
> +	vbus-supply = <&vbus>;
> +	status = "okay";
> +};
> +
> +&usb3_1 {
> +	status = "okay";
> +};
> +
> +&usb_dwc3_0 {
> +	dr_mode = "host";
> +};
> +
> +&usb_dwc3_1 {
> +	dr_mode = "host";
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&usdhc2_pins>;
> +	pinctrl-1 = <&usdhc2_100mhz_pins>;
> +	pinctrl-2 = <&usdhc2_200mhz_pins>;
> +	vmmc-supply = <&vmmc>;
> +	bus-width = <4>;
> +	cap-power-off-card;
> +	full-pwr-cycle;
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..a7ee0a4d4f765581dbc27d3c5dfc656b026d27e6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
> @@ -0,0 +1,591 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +#include "imx8mp.dtsi"
> +
> +/ {
> +	model = "SolidRun i.MX8MP SoM";
> +	compatible = "solidrun,imx8mp-sr-som", "fsl,imx8mp";
> +
> +	chosen {
> +		bootargs = "earlycon=ec_imx6q,0x30890000,115200";
> +		stdout-path = &uart2;
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000 0 0xc0000000>,
> +		      <0x1 0x00000000 0 0xc0000000>;
> +	};
> +
> +	usdhc1_pwrseq: usdhc1-pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
> +	};
> +
> +	v_1_8: regulator-1-8 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "1v8";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +	};
> +
> +	v_3_3: regulator-3-3 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "3v3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};
> +};
> +
> +&eqos {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&eqos_pins>, <&phy0_pins>;
> +	phy-mode = "rgmii-id";
> +	phy = <&phy0>;
> +	snps,force_thresh_dma_mode;
> +	snps,mtl-tx-config = <&mtl_tx_setup>;
> +	snps,mtl-rx-config = <&mtl_rx_setup>;
> +	status = "okay";
> +
> +	mdio {
> +		compatible = "snps,dwmac-mdio";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		phy0: ethernet-phy@0 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <0>;
> +			reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
> +			interrupt-parent = <&gpio4>;
> +			interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
> +		};
> +	};
> +
> +	mtl_tx_setup: tx-queues-config {
> +		snps,tx-queues-to-use = <5>;
> +
> +		queue0 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0x1>;
> +		};
> +
> +		queue1 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0x2>;
> +		};
> +
> +		queue2 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0x4>;
> +		};
> +
> +		queue3 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0x8>;
> +		};
> +
> +		queue4 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0xf0>;
> +		};
> +	};
> +
> +	mtl_rx_setup: rx-queues-config {
> +		snps,rx-queues-to-use = <5>;
> +		snps,rx-sched-sp;
> +
> +		queue0 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0x1>;
> +			snps,map-to-dma-channel = <0>;
> +		};
> +
> +		queue1 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0x2>;
> +			snps,map-to-dma-channel = <1>;
> +		};
> +
> +		queue2 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0x4>;
> +			snps,map-to-dma-channel = <2>;
> +		};
> +
> +		queue3 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0x8>;
> +			snps,map-to-dma-channel = <3>;
> +		};
> +
> +		queue4 {
> +			snps,dcb-algorithm;
> +			snps,priority = <0xf0>;
> +			snps,map-to-dma-channel = <4>;
> +		};
> +	};
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&fec_pins>, <&phy1_pins>;
> +	phy-mode = "rgmii-id";
> +	phy = <&phy1>;
> +	fsl,magic-packet;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		phy1: ethernet-phy@1 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <0x1>;
> +			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
> +			interrupt-parent = <&gpio4>;
> +			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> +		};
> +	};
> +};
> +
> +&i2c1 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&i2c1_pins>;
> +	pinctrl-1 = <&i2c1_gpio_pins>;
> +	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +
> +	som_eeprom: eeprom@50{
> +		compatible = "st,24c01", "atmel,24c01";
> +		reg = <0x50>;
> +		pagesize = <16>;
> +	};
> +
> +	pmic: pmic@25 {

Sort I2C devices in slave address.

> +		compatible = "nxp,pca9450c";
> +		reg = <0x25>;
> +		pinctrl-0 = <&pmic_pins>;
> +		pinctrl-names = "default";
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <3 GPIO_ACTIVE_LOW>;
> +		nxp,i2c-lt-enable;
> +
> +		regulators {
> +			buck1: BUCK1 {
> +				regulator-name = "BUCK1";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <2187500>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			buck2: BUCK2 {
> +				regulator-name = "BUCK2";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <2187500>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +				nxp,dvs-run-voltage = <950000>;
> +				nxp,dvs-standby-voltage = <850000>;
> +			};
> +
> +			buck4: BUCK4{
> +				regulator-name = "BUCK4";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck5: BUCK5{
> +				regulator-name = "BUCK5";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck6: BUCK6 {
> +				regulator-name = "BUCK6";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo1: LDO1 {
> +				regulator-name = "LDO1";
> +				regulator-min-microvolt = <1600000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo2: LDO2 {
> +				regulator-name = "LDO2";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1150000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo3: LDO3 {
> +				regulator-name = "LDO3";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo4: LDO4 {
> +				regulator-name = "LDO4";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo5: LDO5 {
> +				regulator-name = "LDO5";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&i2c2_pins>;
> +	pinctrl-1 = <&i2c2_gpio_pins>;
> +	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +};
> +
> +&i2c3 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&i2c3_pins>;
> +	pinctrl-1 = <&i2c3_gpio_pins>;
> +	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +};
> +
> +&i2c4 {
> +	/* routed to basler camera connector */
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&i2c4_pins>;
> +	pinctrl-1 = <&i2c4_gpio_pins>;
> +	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	eqos_pins: pinctrl-eqos-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
> +			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
> +			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
> +			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
> +			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
> +			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
> +			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
> +			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
> +			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
> +			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
> +			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
> +			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
> +			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
> +			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
> +		>;
> +	};
> +
> +	fec_pins: pinctrl-fec-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
> +			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
> +			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
> +			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
> +			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
> +			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
> +			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
> +			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
> +			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
> +			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
> +			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
> +			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
> +			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
> +			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
> +		>;
> +	};
> +
> +	i2c1_pins: pinctrl-i2c1-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3
> +			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c3
> +		>;
> +	};
> +
> +	i2c1_gpio_pins: pinctrl-i2c1-gpio-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c3
> +			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c3
> +		>;
> +	};
> +
> +	i2c2_pins: pinctrl-i2c2-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
> +			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
> +		>;
> +	};
> +
> +	i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c3
> +			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c3
> +		>;
> +	};
> +
> +	i2c3_pins: pinctrl-i2c3-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
> +			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
> +		>;
> +	};
> +
> +	i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c3
> +			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c3
> +		>;
> +	};
> +
> +	i2c4_pins: pinctrl-i2c4-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3
> +			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3
> +		>;
> +	};
> +
> +	i2c4_gpio_pins: pinctrl-i2c4-gpio-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20			0x400001c3
> +			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21			0x400001c3
> +		>;
> +	};
> +
> +	phy0_pins: pinctrl-phy0-grp {
> +		fsl,pins = <
> +			/* RESET_N: weak i/o, open drain, external 1k pull-up */
> +			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x20
> +			/* INT_N: weak i/o, open drain, internal pull-up */
> +			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x160
> +		>;
> +	};
> +
> +	phy1_pins: pinctrl-phy-1-grp {
> +		fsl,pins = <
> +			/* RESET_N: weak i/o, open drain, external 1k pull-up */
> +			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x20
> +			/* INT_N: weak i/o, open drain, internal pull-up */
> +			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x160
> +		>;
> +	};
> +
> +	pmic_pins: pinctrl-pmic-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41
> +		>;
> +	};
> +
> +	uart1_pins: pinctrl-uart1-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x140
> +			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x140
> +			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS		0x140
> +			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS		0x140
> +			/* BT_REG_ON */
> +			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x0
> +			/* BT_WAKE_DEV */
> +			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x0
> +			/* BT_WAKE_HOST */
> +			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x100
> +		>;
> +	};
> +
> +	uart2_pins: pinctrl-uart2-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
> +			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
> +		>;
> +	};
> +
> +	usdhc1_pins: pinctrl-usdhc1-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
> +			/* WL_REG_ON */
> +			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x0
> +			/* WL_WAKE_HOST */
> +			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x100
> +		>;
> +	};
> +
> +	usdhc1_100mhz_pins: pinctrl-usdhc1g-100mhz-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
> +		>;
> +	};
> +
> +	usdhc1_200mhz_pins: pinctrl-usdhc1-200mhz-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
> +		>;
> +	};
> +
> +	usdhc3_pins: pinctrl-usdhc3-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
> +		>;
> +	};
> +
> +	usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
> +		>;
> +	};
> +
> +	usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
> +		>;
> +	};
> +
> +	wdog1_pins: pinctrl-wdog1-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0x140
> +		>;
> +	};
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart1_pins>;
> +	uart-has-rtscts;
> +	/* select 80MHz parent clock to support maximum baudrate 4Mbps */
> +	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> +	status = "okay";
> +
> +	bluetooth {
> +		compatible = "brcm,bcm4345c5";
> +		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
> +		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
> +		shutdown-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
> +		/* Murata 1MW module supports max. 3M baud */
> +		max-speed = <3000000>;
> +	};
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart2_pins>;
> +	status = "okay";
> +};
> +
> +&usdhc1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&usdhc1_pins>;
> +	pinctrl-1 = <&usdhc1_100mhz_pins>;
> +	pinctrl-2 = <&usdhc1_200mhz_pins>;
> +	vmmc-supply = <&v_3_3>;
> +	vqmmc-supply = <&v_1_8>;
> +	bus-width = <4>;
> +	mmc-pwrseq = <&usdhc1_pwrseq>;
> +	status = "okay";
> +};
> +
> +&usdhc3 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&usdhc3_pins>;
> +	pinctrl-1 = <&usdhc3_100mhz_pins>;
> +	pinctrl-2 = <&usdhc3_200mhz_pins>;
> +	vmmc-supply = <&v_3_3>;
> +	vqmmc-supply = <&v_1_8>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&wdog1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&wdog1_pins>;
> +	status = "okay";
> +};
> +
> +/*
> + * Reserve all physical memory from within the first 1GB of DDR address
> + * space to avoid panic on low memory systems.
> + */
> +&dsp_reserved {

Can we  place this node in order too?

Shawn

> +	reg = <0 0x6f000000 0 0x1000000>;
> +};
> 
> -- 
> 2.43.0
> 


^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: add description for solidrun imx8mp hummingboard variants
  2025-07-07 16:11 ` [PATCH v2 3/3] arm64: dts: add description for solidrun imx8mp hummingboard variants Josua Mayer
@ 2025-07-11  8:01   ` Shawn Guo
  0 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2025-07-11  8:01 UTC (permalink / raw)
  To: Josua Mayer
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	Yazan Shhady, Mikhail Anikin, Jon Nettleton, devicetree,
	linux-kernel, imx, linux-arm-kernel

On Mon, Jul 07, 2025 at 07:11:58PM +0300, Josua Mayer wrote:
> Add descriptions for the SolidRun i.MX8M Plus System on Module based
> HummingBoard product-line. They share a common designed based on the
> "Pulse" version, defined by various assembly options.
> 
> The HummingBoard Pulse features:
> - 2x RJ45 Ethernet
> - 2x USB-3.0 Type A
> - HDMI connector
> - mini-HDMI connector
> - microSD connector
> - mini-PCI-E connector with SIM slot supporting USB-2.0/3.0 interfaces
> - M.2 connector with SIM slot supporting USB-2.0/3.0 interfaces
> - MIPI-CSI Camera Connector (not described without specific camera)
> - 3.5mm Analog Stereo Out / Microphone In Headphone Jack
> - RTC with backup battery
> 
> The variants Mate and Ripple are reduced versions of Pulse.
> 
> The HummingBoard Pro extends Pulse with PCI-E on M.2 connector.
> 
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
>  arch/arm64/boot/dts/freescale/Makefile             |   4 +
>  .../dts/freescale/imx8mp-hummingboard-mate.dts     |  31 ++
>  .../boot/dts/freescale/imx8mp-hummingboard-pro.dts |  76 ++++
>  .../freescale/imx8mp-hummingboard-pulse-codec.dtsi |  59 ++++
>  .../imx8mp-hummingboard-pulse-common.dtsi          | 384 +++++++++++++++++++++
>  .../freescale/imx8mp-hummingboard-pulse-hdmi.dtsi  |  44 +++
>  .../freescale/imx8mp-hummingboard-pulse-m2con.dtsi |  60 ++++
>  .../imx8mp-hummingboard-pulse-mini-hdmi.dtsi       |  81 +++++
>  .../dts/freescale/imx8mp-hummingboard-pulse.dts    |  84 +++++
>  .../dts/freescale/imx8mp-hummingboard-ripple.dts   |  31 ++
>  10 files changed, 854 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index e98c15eb949957a193eb3a7612f3f0f2b04790af..ccc1d6f98495589cb6a55b198d1933bcf076fcb8 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -203,6 +203,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..00614f5d58ea9de51aad9a5f36212dc3d4f3ecaf
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mp-sr-som.dtsi"
> +#include "imx8mp-hummingboard-pulse-common.dtsi"
> +#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
> +
> +/ {
> +	model = "SolidRun i.MX8MP HummingBoard Mate";
> +	compatible = "solidrun,imx8mp-hummingboard-mate",
> +		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
> +
> +	aliases {
> +		ethernet0 = &eqos;
> +		/delete-property/ ethernet1;
> +	};
> +};
> +
> +&fec {
> +	/* this board does not use second phy / ethernet on SoM */
> +	status = "disabled";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..36cd452f1583987a1e826d33798d9aecaaf21568
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
> +
> +#include "imx8mp-sr-som.dtsi"
> +#include "imx8mp-hummingboard-pulse-codec.dtsi"
> +#include "imx8mp-hummingboard-pulse-common.dtsi"
> +#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
> +#include "imx8mp-hummingboard-pulse-m2con.dtsi"
> +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
> +
> +/ {
> +	model = "SolidRun i.MX8MP HummingBoard Pro";
> +	compatible = "solidrun,imx8mp-hummingboard-pro",
> +		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
> +
> +	aliases {
> +		ethernet0 = &eqos;
> +		ethernet1 = &fec;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>,
> +		    <&m2_wwan_wake_pins>;
> +};
> +
> +&pcie {
> +	pinctrl-0 = <&m2_reset_pins>;
> +	pinctrl-names = "default";
> +	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +};
> +
> +&pcie_phy {
> +	clocks = <&hsio_blk_ctrl>;
> +	clock-names = "ref";
> +	fsl,clkreq-unsupported;
> +	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
> +	status = "okay";
> +};
> +
> +&phy0 {
> +	leds {
> +		/* ADIN1300 LED_0 pin */
> +		led@0 {
> +			reg = <0>;
> +			color = <LED_COLOR_ID_ORANGE>;
> +			function = LED_FUNCTION_LAN;
> +			default-state = "keep";
> +		};
> +
> +		/delete-node/ led@1;
> +	};
> +};
> +
> +&phy1 {
> +	leds {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		/* ADIN1300 LED_0 pin */
> +		led@0 {
> +			reg = <0>;
> +			color = <LED_COLOR_ID_GREEN>;
> +			function = LED_FUNCTION_LAN;
> +			default-state = "keep";
> +		};
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..fd16916676db4ec6f0e66d9c52355c37fe06b971
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/ {
> +	sound-wm8904 {
> +		compatible = "fsl,imx-audio-wm8904";
> +		model = "audio-wm8904";
> +		audio-cpu = <&sai3>;
> +		audio-codec = <&codec>;
> +		audio-routing =
> +			"Headphone Jack", "HPOUTL",
> +			"Headphone Jack", "HPOUTR",
> +			"AMIC", "MICBIAS",
> +			"IN2R", "AMIC";
> +	};
> +};
> +
> +&i2c2 {
> +	codec: codec@1a {

audio-codec for the node name.

> +		#sound-dai-cells = <0>;
> +		compatible = "wlf,wm8904";
> +		reg = <0x1a>;

Can we move "#sound-dai-cells" here?  We usually start with "compatible"
and "reg".

> +		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
> +		clock-names = "mclk";
> +		AVDD-supply = <&v_1_8>;
> +		CPVDD-supply = <&v_1_8>;
> +		DBVDD-supply = <&v_3_3>;
> +		DCVDD-supply = <&v_1_8>;
> +		MICVDD-supply = <&v_3_3>;
> +	};
> +};
> +
> +&iomuxc {
> +	sai3_pins: pinctrl-sai3-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6
> +			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
> +			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
> +			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
> +			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
> +		>;
> +	};
> +};
> +
> +&sai3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&sai3_pins>;
> +	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
> +	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
> +	assigned-clock-rates = <12288000>;
> +	clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
> +		 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
> +		 <&clk IMX8MP_CLK_DUMMY>;
> +	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> +	fsl,sai-mclk-direction-output;
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..3a43cf3e2ca00741fe15cd834df0ac7c9119ad09
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi
> @@ -0,0 +1,384 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +	aliases {
> +		rtc0 = &carrier_rtc;
> +		rtc1 = &snvs_rtc;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&led_pins>;
> +
> +		led-0 {
> +			label = "D30";
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
> +			default-state = "on";
> +		};
> +
> +		led-1 {
> +			label = "D31";
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
> +			default-state = "on";
> +		};
> +
> +		led-2 {
> +			label = "D32";
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
> +			default-state = "on";
> +		};
> +
> +		led-3 {
> +			label = "D33";
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
> +			default-state = "on";
> +		};
> +
> +		led-4 {
> +			label = "D34";
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> +			default-state = "on";
> +		};
> +	};
> +
> +	rfkill-mpcie-wifi {
> +		/*
> +		 * The mpcie connector only has USB,
> +		 * therefore this rfkill is for cellular radios only.
> +		 */
> +		compatible = "rfkill-gpio";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&mpcie_rfkill_pins>;
> +		label = "mpcie radio";
> +		radio-type = "wwan";
> +		/* rfkill-gpio inverts internally */
> +		shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	vmmc: regulator-mmc {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vmmc_pins>;
> +		regulator-name = "vmmc";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> +		startup-delay-us = <250>;
> +	};
> +
> +	vbus1: regulator-vbus-1 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vbus1";
> +		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vbus1_pins>;
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +	};
> +
> +	vbus2: regulator-vbus-2 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vbus2";
> +		gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vbus2_pins>;
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +	};
> +
> +	v_1_2: regulator-1-2 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "1v2";
> +		regulator-min-microvolt = <1200000>;
> +		regulator-max-microvolt = <1200000>;
> +	};
> +
> +	vmpcie {
> +		/* supplies mpcie and m2 connectors */
> +		compatible = "regulator-fixed";
> +		regulator-name = "vmpcie";
> +		gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vmpcie_pins>;
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +	};
> +};
> +
> +/* mikrobus spi */
> +&ecspi2 {
> +	num-cs = <1>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mikro_spi_pins>;
> +	status = "okay";
> +};
> +
> +&gpio1 {
> +	pinctrl-0 = <&mpcie_reset_pins>;
> +	pinctrl-names = "default";
> +
> +	mpcie-reset-hog {
> +		gpio-hog;
> +		gpios = <1 GPIO_ACTIVE_LOW>;
> +		output-low;
> +		line-name = "mpcie-reset";
> +	};
> +};
> +
> +&i2c3 {
> +	carrier_rtc: rtc@69 {
> +		compatible = "abracon,ab1805";
> +		reg = <0x69>;
> +		abracon,tc-diode = "schottky";
> +		abracon,tc-resistor = <3>;
> +	};
> +
> +	carrier_eeprom: eeprom@57{

Sort I2C devices in slave address.

> +		compatible = "st,24c02", "atmel,24c02";
> +		reg = <0x57>;
> +		pagesize = <16>;
> +	};
> +};
> +
> +&iomuxc {
> +	csi_pins: pinctrl-csi-grp {
> +		fsl,pins = <
> +			/* Pin 24: STROBE */
> +			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07		0x0
> +		>;
> +	};
> +
> +	mikro_int_pins: pinctrl-mikro-int-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x0
> +		>;
> +	};
> +
> +	mikro_pwm_pins: pinctrl-mikro-pwm-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08		0x0
> +		>;
> +	};
> +
> +	mikro_rst_pins: pinctrl-mikro-rst-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x0
> +		>;
> +	};
> +
> +	mikro_spi_pins: pinctrl-mikro-spi-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0		0x40000
> +			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
> +			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
> +			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
> +		>;
> +	};
> +
> +	mikro_uart_pins: pinctrl-mikro-uart-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
> +			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
> +		>;
> +	};
> +
> +	led_pins: pinctrl-led-grp {

This one is out of order?

> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x0
> +			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x0
> +			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23		0x0
> +			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24		0x0
> +			MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28		0x0
> +		>;
> +	};
> +
> +	mpcie_reset_pins: pinctrl-mpcie-reset-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x0
> +		>;
> +	};
> +
> +	mpcie_rfkill_pins: pinctrl-pcie-rfkill-grp {
> +		fsl,pins = <
> +			/* weak i/o, open drain */
> +			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x20
> +		>;
> +	};
> +
> +	usb_hub_pins: pinctrl-usb-hub-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x0
> +		>;
> +	};
> +
> +	usdhc2_pins: pinctrl-usdhc2-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
> +		>;
> +	};
> +
> +	usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
> +		>;
> +	};
> +
> +	usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
> +		>;
> +	};
> +
> +	vbus1_pins: pinctrl-vbus-1-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x20
> +		>;
> +	};
> +
> +	vbus2_pins: pinctrl-vbus-2-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x20
> +		>;
> +	};
> +
> +	vmmc_pins: pinctrl-vmmc-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41
> +		>;
> +	};
> +
> +	vmpcie_pins: pinctrl-vmpcie-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x0
> +		>;
> +	};
> +};
> +
> +&phy0 {
> +	leds {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		/* ADIN1300 LED_0 pin */
> +		led@0 {
> +			reg = <0>;
> +			color = <LED_COLOR_ID_ORANGE>;
> +			function = LED_FUNCTION_LAN;
> +			default-state = "keep";
> +		};
> +
> +		/* ADIN1300 LINK_ST pin */
> +		led@1 {
> +			reg = <1>;
> +			color = <LED_COLOR_ID_GREEN>;
> +			function = LED_FUNCTION_LAN;
> +			default-state = "keep";
> +		};
> +	};
> +};
> +
> +&snvs_pwrkey {
> +	status = "okay";
> +};
> +
> +/* mikrobus uart */
> +&uart3 {
> +	status = "okay";
> +};
> +
> +&usb3_phy0 {
> +	fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
> +	vbus-supply = <&vbus2>;
> +	status = "okay";
> +};
> +
> +&usb3_0 {
> +	status = "okay";
> +};
> +
> +&usb3_phy1 {
> +	vbus-supply = <&vbus1>;
> +	status = "okay";
> +};
> +
> +&usb3_1 {
> +	status = "okay";
> +};
> +
> +&usb_dwc3_0 {
> +	dr_mode = "host";
> +};
> +
> +&usb_dwc3_1 {
> +	dr_mode = "host";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&usb_hub_pins>;
> +
> +	hub_2_0: hub@1 {
> +		compatible = "usb4b4,6502", "usb4b4,6506";
> +		reg = <1>;
> +		peer-hub = <&hub_3_0>;
> +		reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
> +		vdd-supply = <&v_1_2>;
> +		vdd2-supply = <&v_3_3>;
> +	};
> +
> +	hub_3_0: hub@2 {
> +		compatible = "usb4b4,6500", "usb4b4,6504";
> +		reg = <2>;
> +		peer-hub = <&hub_2_0>;
> +		reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
> +		vdd-supply = <&v_1_2>;
> +		vdd2-supply = <&v_3_3>;
> +	};
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&usdhc2_pins>;
> +	pinctrl-1 = <&usdhc2_100mhz_pins>;
> +	pinctrl-2 = <&usdhc2_200mhz_pins>;
> +	vmmc-supply = <&vmmc>;
> +	bus-width = <4>;
> +	cap-power-off-card;
> +	full-pwr-cycle;
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..d7a999c0d7e06a8c47a61632a59eb97faea9e3d4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/ {
> +	sound-hdmi {
> +		compatible = "fsl,imx-audio-hdmi";
> +		model = "audio-hdmi";
> +		audio-cpu = <&aud2htx>;
> +		hdmi-out;
> +	};
> +};
> +
> +&aud2htx {
> +	status = "okay";
> +};
> +
> +&hdmi_pvi {
> +	status = "okay";
> +};
> +
> +&hdmi_tx {
> +	status = "okay";
> +};
> +
> +&hdmi_tx_phy {
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	hdmi_pins: pinctrl-hdmi-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
> +			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
> +			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
> +			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
> +		>;
> +	};
> +};
> +
> +&lcdif3 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..b879ca4ed21428b8d4c6866f9a827bcfbef1caee
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/ {
> +	rfkill-m2-gnss {
> +		compatible = "rfkill-gpio";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&m2_gnss_rfkill_pins>;
> +		label = "m.2 GNSS";
> +		radio-type = "gps";
> +		/* rfkill-gpio inverts internally */
> +		shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	/* M.2 is B-keyed, so w-disable is for WWAN */
> +	rfkill-m2-wwan {
> +		compatible = "rfkill-gpio";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&m2_wwan_rfkill_pins>;
> +		label = "m.2 WWAN";
> +		radio-type = "wwan";
> +		/* rfkill-gpio inverts internally */
> +		shutdown-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +&iomuxc {
> +	m2_gnss_rfkill_pins: pinctrl-m2-gnss-rfkill-grp {
> +		fsl,pins = <
> +			/* weak i/o, open drain */
> +			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x20
> +		>;
> +	};
> +
> +	m2_wwan_rfkill_pins: pinctrl-m2-wwan-rfkill-grp {
> +		fsl,pins = <
> +			/* weak i/o, open drain */
> +			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x20
> +		>;
> +	};
> +
> +	m2_wwan_wake_pins: pinctrl-m2-wwan-wake-grp {
> +		fsl,pins = <
> +			/* weak i/o, open drain */
> +			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x20
> +		>;
> +	};
> +
> +	m2_reset_pins: pinctrl-m2-reset-grp {

This one is out of order?

> +		fsl,pins = <
> +			/*
> +			 * 3.3V domain on SoC, set open-drain to ensure
> +			 * 1.8V logic on connector
> +			 */
> +			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x20
> +		>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..46916ddc053355b6708629898fa13e55c6493cc2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/ {
> +	hdmi-connector {
> +		compatible = "hdmi-connector";
> +		label = "hdmi";
> +		type = "c";
> +
> +		port {
> +			hdmi_connector_in: endpoint {
> +				remote-endpoint = <&adv7535_out>;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c3 {
> +	hdmi@3d {
> +		compatible = "adi,adv7535";
> +		reg = <0x3d>, <0x3f>, <0x3c>, <0x38>;
> +		reg-names = "main", "edid", "cec", "packet";
> +		adi,dsi-lanes = <4>;
> +		avdd-supply = <&v_1_8>;
> +		dvdd-supply = <&v_1_8>;
> +		pvdd-supply = <&v_1_8>;
> +		a2vdd-supply = <&v_1_8>;
> +		v3p3-supply = <&v_3_3>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&mini_hdmi_pins>;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@0 {
> +				reg = <0>;
> +
> +				adv7535_from_dsim: endpoint {
> +					remote-endpoint = <&dsim_to_adv7535>;
> +				};
> +			};
> +
> +			port@1 {
> +				reg = <1>;
> +
> +				adv7535_out: endpoint {
> +					remote-endpoint = <&hdmi_connector_in>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&iomuxc {
> +	mini_hdmi_pins: pinctrl-mini-hdmi-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x0
> +		>;
> +	};
> +};
> +
> +&lcdif1 {
> +	status = "okay";
> +};
> +
> +&mipi_dsi {
> +	samsung,esc-clock-frequency = <10000000>;
> +	status = "okay";
> +
> +	port@1 {
> +		dsim_to_adv7535: endpoint {
> +			remote-endpoint = <&adv7535_from_dsim>;
> +			attach-bridge;
> +		};
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..e0d6f281837f106bb0b4661d8fe54eaa2cafc3c2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
> +
> +#include "imx8mp-sr-som.dtsi"
> +#include "imx8mp-hummingboard-pulse-codec.dtsi"
> +#include "imx8mp-hummingboard-pulse-common.dtsi"
> +#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
> +#include "imx8mp-hummingboard-pulse-m2con.dtsi"
> +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
> +
> +/ {
> +	model = "SolidRun i.MX8MP HummingBoard Pulse";
> +	compatible = "solidrun,imx8mp-hummingboard-pulse",
> +		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
> +
> +	aliases {
> +		ethernet0 = &eqos;
> +		ethernet1 = &pcie_eth;
> +	};
> +};
> +
> +&fec {
> +	/* this board does not use second phy / ethernet on SoM */
> +	status = "disabled";
> +};
> +
> +&gpio1 {
> +	pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>;
> +	pinctrl-names = "default";
> +
> +	m2-reset-hog {
> +		gpio-hog;
> +		gpios = <6 GPIO_ACTIVE_LOW>;
> +		output-low;
> +		line-name = "m2-reset";
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>,
> +		    <&m2_wwan_wake_pins>;
> +
> +	pcie_eth_pins: pinctrl-pcie-eth-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x0
> +		>;
> +	};
> +};
> +
> +&pcie {
> +	pinctrl-0 = <&pcie_eth_pins>;
> +	pinctrl-names = "default";
> +	reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +
> +	root@0,0 {
> +		compatible = "pci16c3,abcd";
> +		reg = <0x00000000 0 0 0 0>;
> +

Nit: unnecessary newline

Shawn

> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +
> +		/* Intel i210 */
> +		pcie_eth: ethernet@1,0 {
> +			compatible = "pci8086,157b";
> +			reg = <0x00010000 0 0 0 0>;
> +		};
> +	};
> +};
> +
> +&pcie_phy {
> +	clocks = <&hsio_blk_ctrl>;
> +	clock-names = "ref";
> +	fsl,clkreq-unsupported;
> +	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..4ce5b799b6abc514ca00e2e2134d5ff1606dc87d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mp-sr-som.dtsi"
> +#include "imx8mp-hummingboard-pulse-common.dtsi"
> +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
> +
> +/ {
> +	model = "SolidRun i.MX8MP HummingBoard Ripple";
> +	compatible = "solidrun,imx8mp-hummingboard-ripple",
> +		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
> +
> +	aliases {
> +		ethernet0 = &eqos;
> +		/delete-property/ ethernet1;
> +	};
> +};
> +
> +&fec {
> +	/* this board does not use second phy / ethernet on SoM */
> +	status = "disabled";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>;
> +};
> 
> -- 
> 2.43.0
> 


^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: add description for solidrun imx8mp som and cubox-m
  2025-07-11  7:49   ` Shawn Guo
@ 2025-07-13 11:15     ` Josua Mayer
  0 siblings, 0 replies; 7+ messages in thread
From: Josua Mayer @ 2025-07-13 11:15 UTC (permalink / raw)
  To: Shawn Guo
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	Yazan Shhady, Mikhail Anikin, Jon Nettleton,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org

On 11/07/2025 10:49, Shawn Guo wrote:
> On Mon, Jul 07, 2025 at 07:11:57PM +0300, Josua Mayer wrote:
>> Add description for the SolidRun i.MX8M Plus based System on Module, and
>> the CuBox-M.
>>
>> The SoM features:
>> - 2x 1Gbps Ethernet with PHY
>> - eMMC
>> - 1/2/3/8GB DDR
>> - MIPI-CSI Camera Connector (not described without specific camera)
>>
>> The CuBox-M is a complete product with enclosure featuring:
>> - 1x 1Gbps RJ45 Ethernet Port
>> - 2x USB-3.0 Type A
>> - HDMI connector
>> - microSD connector
>> - microUSB connector for console (using fdtdi chip)
>> - IR receiver
>> - RTC with backup battery
>>
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>> ---
>>   arch/arm64/boot/dts/freescale/Makefile           |   1 +
>>   arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts | 224 +++++++++
>>   arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 591 +++++++++++++++++++++++
>>   3 files changed, 816 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
>> index 0b473a23d12008ff79d6467d9e1c7ab2c4d6a9a6..e98c15eb949957a193eb3a7612f3f0f2b04790af 100644
>> --- a/arch/arm64/boot/dts/freescale/Makefile
>> +++ b/arch/arm64/boot/dts/freescale/Makefile
>> @@ -194,6 +194,7 @@ imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-
>>   dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb
>>   dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
>>   dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
>> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb
>>   dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
>>   dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
>>   dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..13da5e0196a3fc168efdde63d86f0fe776f999fb
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
>> @@ -0,0 +1,224 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/leds/common.h>
>> +
>> +#include "imx8mp-sr-som.dtsi"
>> +
>> +/ {
>> +	model = "SolidRun i.MX8MP CuBox-M";
>> +	compatible = "solidrun,imx8mp-cubox-m",
>> +		     "solidrun,imx8mp-sr-som", "fsl,imx8mp";
>> +
>> +	aliases {
>> +		ethernet0 = &eqos;
>> +		/delete-property/ ethernet1;
>> +		rtc0 = &carrier_rtc;
>> +		rtc1 = &snvs_rtc;
>> +	};
>> +
>> +	ir-receiver {
>> +		compatible = "gpio-ir-receiver";
>> +		gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&ir_pins>;
>> +		linux,autosuspend-period = <125>;
>> +		wakeup-source;
>> +	};
>> +
>> +	leds {
>> +		compatible = "gpio-leds";
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&led_pins>;
>> +
>> +		status {
>> +			label = "status";
>> +			color = <LED_COLOR_ID_RED>;
>> +			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
>> +			function = LED_FUNCTION_HEARTBEAT;
>> +		};
>> +	};
>> +
>> +	sound-hdmi {
>> +		compatible = "fsl,imx-audio-hdmi";
>> +		model = "audio-hdmi";
>> +		audio-cpu = <&aud2htx>;
>> +		hdmi-out;
>> +		status = "okay";
> We usually use "okay" to flip a "disabled" device.  It's not required
> here I guess?
Correct, will add in v3.
>
>> +	};
>> +
>> +	vbus: regulator-vbus {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "vbus";
>> +		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
>> +		enable-active-high;
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&vbus_pins>;
>> +		regulator-min-microvolt = <5000000>;
>> +		regulator-max-microvolt = <5000000>;
>> +	};
>> +
>> +	vmmc: regulator-mmc {
>> +		compatible = "regulator-fixed";
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&vmmc_pins>;
>> +		regulator-name = "vmmc";
>> +		regulator-min-microvolt = <3300000>;
>> +		regulator-max-microvolt = <3300000>;
>> +		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> +		startup-delay-us = <250>;
>> +	};
>> +};
>> +
>> +&aud2htx {
>> +	status = "okay";
>> +};
>> +
>> +&fec {
>> +	/* this board does not use second phy / ethernet on SoM */
>> +	status = "disabled";
>> +};
>> +
>> +&hdmi_pvi {
>> +	status = "okay";
>> +};
>> +
>> +&hdmi_tx {
>> +	status = "okay";
>> +};
>> +
>> +&hdmi_tx_phy {
>> +	status = "okay";
>> +};
>> +
>> +&i2c3 {
>> +	carrier_rtc: rtc@32 {
>> +		compatible = "epson,rx8130";
>> +		reg = <0x32>;
>> +	};
>> +};
>> +
>> +&iomuxc {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&hdmi_pins>;
>> +
>> +	hdmi_pins: pinctrl-hdmi-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
>> +			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
>> +			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
>> +			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
>> +		>;
>> +	};
>> +
>> +	ir_pins: pinctrl-ir-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x4f
>> +		>;
>> +	};
>> +
>> +	led_pins: pinctrl-led-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x0
>> +		>;
>> +	};
>> +
>> +	usdhc2_pins: pinctrl-usdhc2-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
>> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
>> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
>> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
>> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
>> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
>> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
>> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
>> +		>;
>> +	};
>> +
>> +	usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
>> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
>> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
>> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
>> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
>> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
>> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
>> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
>> +		>;
>> +	};
>> +
>> +	usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
>> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
>> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
>> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
>> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
>> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
>> +			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0x140
>> +			MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B		0x140
>> +		>;
>> +	};
>> +
>> +	vbus_pins: pinctrl-vbus-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x100
>> +		>;
>> +	};
>> +
>> +	vmmc_pins: pinctrl-vmmc-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x0
>> +		>;
>> +	};
>> +};
>> +
>> +&lcdif3 {
>> +	status = "okay";
>> +};
>> +
>> +&usb3_phy0 {
>> +	fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
>> +	vbus-supply = <&vbus>;
>> +	status = "okay";
>> +};
>> +
>> +&usb3_0 {
>> +	status = "okay";
>> +};
>> +
>> +&usb3_phy1 {
>> +	fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
>> +	vbus-supply = <&vbus>;
>> +	status = "okay";
>> +};
>> +
>> +&usb3_1 {
>> +	status = "okay";
>> +};
>> +
>> +&usb_dwc3_0 {
>> +	dr_mode = "host";
>> +};
>> +
>> +&usb_dwc3_1 {
>> +	dr_mode = "host";
>> +};
>> +
>> +&usdhc2 {
>> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> +	pinctrl-0 = <&usdhc2_pins>;
>> +	pinctrl-1 = <&usdhc2_100mhz_pins>;
>> +	pinctrl-2 = <&usdhc2_200mhz_pins>;
>> +	vmmc-supply = <&vmmc>;
>> +	bus-width = <4>;
>> +	cap-power-off-card;
>> +	full-pwr-cycle;
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..a7ee0a4d4f765581dbc27d3c5dfc656b026d27e6
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
>> @@ -0,0 +1,591 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
>> + */
>> +
>> +#include "imx8mp.dtsi"
>> +
>> +/ {
>> +	model = "SolidRun i.MX8MP SoM";
>> +	compatible = "solidrun,imx8mp-sr-som", "fsl,imx8mp";
>> +
>> +	chosen {
>> +		bootargs = "earlycon=ec_imx6q,0x30890000,115200";
>> +		stdout-path = &uart2;
>> +	};
>> +
>> +	memory@40000000 {
>> +		device_type = "memory";
>> +		reg = <0x0 0x40000000 0 0xc0000000>,
>> +		      <0x1 0x00000000 0 0xc0000000>;
>> +	};
>> +
>> +	usdhc1_pwrseq: usdhc1-pwrseq {
>> +		compatible = "mmc-pwrseq-simple";
>> +		reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
>> +	};
>> +
>> +	v_1_8: regulator-1-8 {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "1v8";
>> +		regulator-min-microvolt = <1800000>;
>> +		regulator-max-microvolt = <1800000>;
>> +	};
>> +
>> +	v_3_3: regulator-3-3 {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "3v3";
>> +		regulator-min-microvolt = <3300000>;
>> +		regulator-max-microvolt = <3300000>;
>> +	};
>> +};
>> +
>> +&eqos {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&eqos_pins>, <&phy0_pins>;
>> +	phy-mode = "rgmii-id";
>> +	phy = <&phy0>;
>> +	snps,force_thresh_dma_mode;
>> +	snps,mtl-tx-config = <&mtl_tx_setup>;
>> +	snps,mtl-rx-config = <&mtl_rx_setup>;
>> +	status = "okay";
>> +
>> +	mdio {
>> +		compatible = "snps,dwmac-mdio";
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		phy0: ethernet-phy@0 {
>> +			compatible = "ethernet-phy-ieee802.3-c22";
>> +			reg = <0>;
>> +			reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
>> +			interrupt-parent = <&gpio4>;
>> +			interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
>> +		};
>> +	};
>> +
>> +	mtl_tx_setup: tx-queues-config {
>> +		snps,tx-queues-to-use = <5>;
>> +
>> +		queue0 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0x1>;
>> +		};
>> +
>> +		queue1 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0x2>;
>> +		};
>> +
>> +		queue2 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0x4>;
>> +		};
>> +
>> +		queue3 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0x8>;
>> +		};
>> +
>> +		queue4 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0xf0>;
>> +		};
>> +	};
>> +
>> +	mtl_rx_setup: rx-queues-config {
>> +		snps,rx-queues-to-use = <5>;
>> +		snps,rx-sched-sp;
>> +
>> +		queue0 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0x1>;
>> +			snps,map-to-dma-channel = <0>;
>> +		};
>> +
>> +		queue1 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0x2>;
>> +			snps,map-to-dma-channel = <1>;
>> +		};
>> +
>> +		queue2 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0x4>;
>> +			snps,map-to-dma-channel = <2>;
>> +		};
>> +
>> +		queue3 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0x8>;
>> +			snps,map-to-dma-channel = <3>;
>> +		};
>> +
>> +		queue4 {
>> +			snps,dcb-algorithm;
>> +			snps,priority = <0xf0>;
>> +			snps,map-to-dma-channel = <4>;
>> +		};
>> +	};
>> +};
>> +
>> +&fec {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&fec_pins>, <&phy1_pins>;
>> +	phy-mode = "rgmii-id";
>> +	phy = <&phy1>;
>> +	fsl,magic-packet;
>> +	status = "okay";
>> +
>> +	mdio {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		phy1: ethernet-phy@1 {
>> +			compatible = "ethernet-phy-ieee802.3-c22";
>> +			reg = <0x1>;
>> +			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
>> +			interrupt-parent = <&gpio4>;
>> +			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>> +		};
>> +	};
>> +};
>> +
>> +&i2c1 {
>> +	clock-frequency = <400000>;
>> +	pinctrl-names = "default", "gpio";
>> +	pinctrl-0 = <&i2c1_pins>;
>> +	pinctrl-1 = <&i2c1_gpio_pins>;
>> +	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +	status = "okay";
>> +
>> +	som_eeprom: eeprom@50{
>> +		compatible = "st,24c01", "atmel,24c01";
>> +		reg = <0x50>;
>> +		pagesize = <16>;
>> +	};
>> +
>> +	pmic: pmic@25 {
> Sort I2C devices in slave address.
will add in v3
>
>> +		compatible = "nxp,pca9450c";
>> +		reg = <0x25>;
>> +		pinctrl-0 = <&pmic_pins>;
>> +		pinctrl-names = "default";
>> +		interrupt-parent = <&gpio1>;
>> +		interrupts = <3 GPIO_ACTIVE_LOW>;
>> +		nxp,i2c-lt-enable;
>> +
>> +		regulators {
>> +			buck1: BUCK1 {
>> +				regulator-name = "BUCK1";
>> +				regulator-min-microvolt = <600000>;
>> +				regulator-max-microvolt = <2187500>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +				regulator-ramp-delay = <3125>;
>> +			};
>> +
>> +			buck2: BUCK2 {
>> +				regulator-name = "BUCK2";
>> +				regulator-min-microvolt = <600000>;
>> +				regulator-max-microvolt = <2187500>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +				regulator-ramp-delay = <3125>;
>> +				nxp,dvs-run-voltage = <950000>;
>> +				nxp,dvs-standby-voltage = <850000>;
>> +			};
>> +
>> +			buck4: BUCK4{
>> +				regulator-name = "BUCK4";
>> +				regulator-min-microvolt = <600000>;
>> +				regulator-max-microvolt = <3400000>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +			};
>> +
>> +			buck5: BUCK5{
>> +				regulator-name = "BUCK5";
>> +				regulator-min-microvolt = <600000>;
>> +				regulator-max-microvolt = <3400000>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +			};
>> +
>> +			buck6: BUCK6 {
>> +				regulator-name = "BUCK6";
>> +				regulator-min-microvolt = <600000>;
>> +				regulator-max-microvolt = <3400000>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +			};
>> +
>> +			ldo1: LDO1 {
>> +				regulator-name = "LDO1";
>> +				regulator-min-microvolt = <1600000>;
>> +				regulator-max-microvolt = <3300000>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +			};
>> +
>> +			ldo2: LDO2 {
>> +				regulator-name = "LDO2";
>> +				regulator-min-microvolt = <800000>;
>> +				regulator-max-microvolt = <1150000>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +			};
>> +
>> +			ldo3: LDO3 {
>> +				regulator-name = "LDO3";
>> +				regulator-min-microvolt = <800000>;
>> +				regulator-max-microvolt = <3300000>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +			};
>> +
>> +			ldo4: LDO4 {
>> +				regulator-name = "LDO4";
>> +				regulator-min-microvolt = <800000>;
>> +				regulator-max-microvolt = <3300000>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +			};
>> +
>> +			ldo5: LDO5 {
>> +				regulator-name = "LDO5";
>> +				regulator-min-microvolt = <1800000>;
>> +				regulator-max-microvolt = <3300000>;
>> +				regulator-boot-on;
>> +				regulator-always-on;
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&i2c2 {
>> +	clock-frequency = <100000>;
>> +	pinctrl-names = "default", "gpio";
>> +	pinctrl-0 = <&i2c2_pins>;
>> +	pinctrl-1 = <&i2c2_gpio_pins>;
>> +	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +	status = "okay";
>> +};
>> +
>> +&i2c3 {
>> +	clock-frequency = <100000>;
>> +	pinctrl-names = "default", "gpio";
>> +	pinctrl-0 = <&i2c3_pins>;
>> +	pinctrl-1 = <&i2c3_gpio_pins>;
>> +	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +	status = "okay";
>> +};
>> +
>> +&i2c4 {
>> +	/* routed to basler camera connector */
>> +	clock-frequency = <100000>;
>> +	pinctrl-names = "default", "gpio";
>> +	pinctrl-0 = <&i2c4_pins>;
>> +	pinctrl-1 = <&i2c4_gpio_pins>;
>> +	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +	status = "okay";
>> +};
>> +
>> +&iomuxc {
>> +	eqos_pins: pinctrl-eqos-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
>> +			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
>> +			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
>> +			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
>> +			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
>> +			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
>> +			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
>> +			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
>> +			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
>> +			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
>> +			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
>> +			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
>> +			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
>> +			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
>> +		>;
>> +	};
>> +
>> +	fec_pins: pinctrl-fec-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
>> +			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
>> +			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
>> +			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
>> +			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
>> +			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
>> +			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
>> +			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
>> +			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
>> +			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
>> +			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
>> +			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
>> +			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
>> +			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
>> +		>;
>> +	};
>> +
>> +	i2c1_pins: pinctrl-i2c1-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3
>> +			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c3
>> +		>;
>> +	};
>> +
>> +	i2c1_gpio_pins: pinctrl-i2c1-gpio-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c3
>> +			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c3
>> +		>;
>> +	};
>> +
>> +	i2c2_pins: pinctrl-i2c2-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
>> +			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
>> +		>;
>> +	};
>> +
>> +	i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c3
>> +			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c3
>> +		>;
>> +	};
>> +
>> +	i2c3_pins: pinctrl-i2c3-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
>> +			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
>> +		>;
>> +	};
>> +
>> +	i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c3
>> +			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c3
>> +		>;
>> +	};
>> +
>> +	i2c4_pins: pinctrl-i2c4-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3
>> +			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3
>> +		>;
>> +	};
>> +
>> +	i2c4_gpio_pins: pinctrl-i2c4-gpio-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20			0x400001c3
>> +			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21			0x400001c3
>> +		>;
>> +	};
>> +
>> +	phy0_pins: pinctrl-phy0-grp {
>> +		fsl,pins = <
>> +			/* RESET_N: weak i/o, open drain, external 1k pull-up */
>> +			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x20
>> +			/* INT_N: weak i/o, open drain, internal pull-up */
>> +			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x160
>> +		>;
>> +	};
>> +
>> +	phy1_pins: pinctrl-phy-1-grp {
>> +		fsl,pins = <
>> +			/* RESET_N: weak i/o, open drain, external 1k pull-up */
>> +			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x20
>> +			/* INT_N: weak i/o, open drain, internal pull-up */
>> +			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x160
>> +		>;
>> +	};
>> +
>> +	pmic_pins: pinctrl-pmic-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41
>> +		>;
>> +	};
>> +
>> +	uart1_pins: pinctrl-uart1-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x140
>> +			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x140
>> +			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS		0x140
>> +			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS		0x140
>> +			/* BT_REG_ON */
>> +			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x0
>> +			/* BT_WAKE_DEV */
>> +			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x0
>> +			/* BT_WAKE_HOST */
>> +			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x100
>> +		>;
>> +	};
>> +
>> +	uart2_pins: pinctrl-uart2-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
>> +			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
>> +		>;
>> +	};
>> +
>> +	usdhc1_pins: pinctrl-usdhc1-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
>> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
>> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
>> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
>> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
>> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
>> +			/* WL_REG_ON */
>> +			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x0
>> +			/* WL_WAKE_HOST */
>> +			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x100
>> +		>;
>> +	};
>> +
>> +	usdhc1_100mhz_pins: pinctrl-usdhc1g-100mhz-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
>> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
>> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
>> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
>> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
>> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
>> +		>;
>> +	};
>> +
>> +	usdhc1_200mhz_pins: pinctrl-usdhc1-200mhz-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
>> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
>> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
>> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
>> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
>> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
>> +		>;
>> +	};
>> +
>> +	usdhc3_pins: pinctrl-usdhc3-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
>> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
>> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
>> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
>> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
>> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
>> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
>> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
>> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
>> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
>> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
>> +		>;
>> +	};
>> +
>> +	usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
>> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
>> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
>> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
>> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
>> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
>> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
>> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
>> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
>> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
>> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
>> +		>;
>> +	};
>> +
>> +	usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
>> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
>> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
>> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
>> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
>> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
>> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
>> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
>> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
>> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
>> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
>> +		>;
>> +	};
>> +
>> +	wdog1_pins: pinctrl-wdog1-grp {
>> +		fsl,pins = <
>> +			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0x140
>> +		>;
>> +	};
>> +};
>> +
>> +&uart1 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart1_pins>;
>> +	uart-has-rtscts;
>> +	/* select 80MHz parent clock to support maximum baudrate 4Mbps */
>> +	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
>> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
>> +	status = "okay";
>> +
>> +	bluetooth {
>> +		compatible = "brcm,bcm4345c5";
>> +		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
>> +		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
>> +		shutdown-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
>> +		/* Murata 1MW module supports max. 3M baud */
>> +		max-speed = <3000000>;
>> +	};
>> +};
>> +
>> +&uart2 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart2_pins>;
>> +	status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&usdhc1_pins>;
>> +	pinctrl-1 = <&usdhc1_100mhz_pins>;
>> +	pinctrl-2 = <&usdhc1_200mhz_pins>;
>> +	vmmc-supply = <&v_3_3>;
>> +	vqmmc-supply = <&v_1_8>;
>> +	bus-width = <4>;
>> +	mmc-pwrseq = <&usdhc1_pwrseq>;
>> +	status = "okay";
>> +};
>> +
>> +&usdhc3 {
>> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> +	pinctrl-0 = <&usdhc3_pins>;
>> +	pinctrl-1 = <&usdhc3_100mhz_pins>;
>> +	pinctrl-2 = <&usdhc3_200mhz_pins>;
>> +	vmmc-supply = <&v_3_3>;
>> +	vqmmc-supply = <&v_1_8>;
>> +	bus-width = <8>;
>> +	non-removable;
>> +	status = "okay";
>> +};
>> +
>> +&wdog1 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&wdog1_pins>;
>> +	status = "okay";
>> +};
>> +
>> +/*
>> + * Reserve all physical memory from within the first 1GB of DDR address
>> + * space to avoid panic on low memory systems.
>> + */
>> +&dsp_reserved {
> Can we  place this node in order too?
We can, the motivation for placing at end is that NXP kernel fork
has lots of reserved memory nodes, and it is more readable
to have them together.

For now I will put the single one in order.
>
> Shawn
>
>> +	reg = <0 0x6f000000 0 0x1000000>;
>> +};
>>
>> -- 
>> 2.43.0
>>


^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-07-13 11:15 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-07-07 16:11 [PATCH v2 0/3] arm64: dts: add descriptions for solidrun i.mx8mp based boards Josua Mayer
2025-07-07 16:11 ` [PATCH v2 1/3] dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards Josua Mayer
2025-07-07 16:11 ` [PATCH v2 2/3] arm64: dts: add description for solidrun imx8mp som and cubox-m Josua Mayer
2025-07-11  7:49   ` Shawn Guo
2025-07-13 11:15     ` Josua Mayer
2025-07-07 16:11 ` [PATCH v2 3/3] arm64: dts: add description for solidrun imx8mp hummingboard variants Josua Mayer
2025-07-11  8:01   ` Shawn Guo

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