From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B549226CFC; Tue, 8 Jul 2025 06:55:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751957753; cv=none; b=HfdlR1u31ch10BVngo6DvLLZ0Dpw/pmrL0SnpXjnD9nr8my/aacckkDfU61Fwk4QfhBMgfmBRqQmAmOvSfP72CbFUJWI9Tub8fhelhPKdPS8sEDIU5UgNSbsG4DWDBaHRdepP8ZsbOkbHvr0WMGYyOFPa5nvH1R2SEDbNMkQ15Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751957753; c=relaxed/simple; bh=YQhsnLUMAU7ZH3pjjQGAg2eqdpC5eflBNrsKckB38kk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dTlOp8b9s3T+an0uMLSt2BKl4XNWPFpr2HfbZlORQbd9rM44gZckck5Vp3vVM1++p/UZG/HKMOAEIJhVKQtFAMfuKv/7s4vh5Y8xmjnd/rD/LZ+Zp+GsfU28BHpRfbOfOAqciUvVc6bIVmp//SO8RpUv/aHruoc6SiEiYT8CyhA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 8 Jul 2025 14:55:44 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 8 Jul 2025 14:55:44 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , , , CC: , Conor Dooley Subject: [net-next v3 2/4] dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2 Date: Tue, 8 Jul 2025 14:55:42 +0800 Message-ID: <20250708065544.201896-3-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250708065544.201896-1-jacky_chou@aspeedtech.com> References: <20250708065544.201896-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Add ASPEED_RESET_MAC1 and ASPEED_RESET_MAC2 reset definitions to the ast2600-clock binding header. These are required for proper reset control of the MAC1 and MAC2 ethernet controllers on the AST2600 SoC. Signed-off-by: Jacky Chou Acked-by: Conor Dooley Acked-by: Stephen Boyd --- include/dt-bindings/clock/ast2600-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 7ae96c7bd72f..f60fff261130 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -122,6 +122,8 @@ #define ASPEED_RESET_PCIE_DEV_OEN 20 #define ASPEED_RESET_PCIE_RC_O 19 #define ASPEED_RESET_PCIE_RC_OEN 18 +#define ASPEED_RESET_MAC2 12 +#define ASPEED_RESET_MAC1 11 #define ASPEED_RESET_PCI_DP 5 #define ASPEED_RESET_HACE 4 #define ASPEED_RESET_AHB 1 -- 2.34.1