From: Conor Dooley <conor@kernel.org>
To: Nick Hu <nick.hu@sifive.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: [PATCH] dt-bindings: riscv: Add SiFive vendor extensions description
Date: Wed, 9 Jul 2025 17:00:39 +0100 [thread overview]
Message-ID: <20250709-startup-coasting-aa58a99c5585@spud> (raw)
In-Reply-To: <20250708065242.26371-1-nick.hu@sifive.com>
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On Tue, Jul 08, 2025 at 02:52:42PM +0800, Nick Hu wrote:
> Add description for SiFive vendor extensions "xsfcflushdlone",
> "xsfpgflushdlone" and "xsfcease".
>
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
You have this, but no user or anything along with it. What's actually
making use of this? If it's just for the SBI impl or w/e then say that.
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 72c1b063fdfe..10c37c61243d 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -626,6 +626,24 @@ properties:
> https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>
> # SiFive
> + - const: xsfcease
> + description:
> + SiFive CEASE Instruction Extensions Specification.
> + See more details in
> + https://www.sifive.com/document-file/freedom-u740-c000-manual
> +
> + - const: xsfcflushdlone
> + description:
> + SiFive L1D Cache Flush Instruction Extensions Specification.
> + See more details in
> + https://www.sifive.com/document-file/freedom-u740-c000-manual
> +
> + - const: xsfpgflushdlone
> + description:
> + SiFive PGFLUSH Instruction Extensions for the power management. The
> + CPU will flush the L1D and enter the cease state after executing
> + the instruction.
> +
> - const: xsfqmaccdod
> description:
> SiFive Int8 Matrix Multiplication Extensions Specification.
> --
> 2.17.1
>
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next prev parent reply other threads:[~2025-07-09 16:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-08 6:52 [PATCH] dt-bindings: riscv: Add SiFive vendor extensions description Nick Hu
2025-07-09 16:00 ` Conor Dooley [this message]
2025-07-10 4:57 ` Nick Hu
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