* [PATCH 2/8] dt-bindings: display: fsl,ldb: Add binding for i.MX94
2025-07-09 12:23 [PATCH 0/8] Add support for i.MX94 DCIF Laurentiu Palcu
@ 2025-07-09 12:23 ` Laurentiu Palcu
2025-07-10 22:15 ` Rob Herring
2025-07-09 12:23 ` [PATCH 5/8] dt-bindings: display: imx: Add bindings for i.MX94 DCIF Laurentiu Palcu
2025-07-09 12:23 ` [PATCH 7/8] arm64: dts: imx943-evk: Add support for DCIF and LVDS Laurentiu Palcu
2 siblings, 1 reply; 8+ messages in thread
From: Laurentiu Palcu @ 2025-07-09 12:23 UTC (permalink / raw)
To: imx, Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Marek Vasut
Cc: dri-devel, Laurentiu Palcu, devicetree, linux-kernel
i.MX94 LDB controller is compatible with i.MX93.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
index 07388bf2b90df..a54b8f1478049 100644
--- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
@@ -20,6 +20,7 @@ properties:
- fsl,imx6sx-ldb
- fsl,imx8mp-ldb
- fsl,imx93-ldb
+ - fsl,imx94-ldb
clocks:
maxItems: 1
@@ -68,6 +69,7 @@ allOf:
enum:
- fsl,imx6sx-ldb
- fsl,imx93-ldb
+ - fsl,imx94-ldb
then:
properties:
ports:
--
2.46.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/8] dt-bindings: display: fsl,ldb: Add binding for i.MX94
2025-07-09 12:23 ` [PATCH 2/8] dt-bindings: display: fsl,ldb: Add binding for i.MX94 Laurentiu Palcu
@ 2025-07-10 22:15 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2025-07-10 22:15 UTC (permalink / raw)
To: Laurentiu Palcu
Cc: imx, Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter,
Krzysztof Kozlowski, Conor Dooley, Marek Vasut, dri-devel,
devicetree, linux-kernel
On Wed, Jul 09, 2025 at 03:23:21PM +0300, Laurentiu Palcu wrote:
> i.MX94 LDB controller is compatible with i.MX93.
That's not what the schema says.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> ---
> Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
> index 07388bf2b90df..a54b8f1478049 100644
> --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
> @@ -20,6 +20,7 @@ properties:
> - fsl,imx6sx-ldb
> - fsl,imx8mp-ldb
> - fsl,imx93-ldb
> + - fsl,imx94-ldb
>
> clocks:
> maxItems: 1
> @@ -68,6 +69,7 @@ allOf:
> enum:
> - fsl,imx6sx-ldb
> - fsl,imx93-ldb
> + - fsl,imx94-ldb
> then:
> properties:
> ports:
> --
> 2.46.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 5/8] dt-bindings: display: imx: Add bindings for i.MX94 DCIF
2025-07-09 12:23 [PATCH 0/8] Add support for i.MX94 DCIF Laurentiu Palcu
2025-07-09 12:23 ` [PATCH 2/8] dt-bindings: display: fsl,ldb: Add binding for i.MX94 Laurentiu Palcu
@ 2025-07-09 12:23 ` Laurentiu Palcu
2025-07-10 22:18 ` Rob Herring
2025-07-09 12:23 ` [PATCH 7/8] arm64: dts: imx943-evk: Add support for DCIF and LVDS Laurentiu Palcu
2 siblings, 1 reply; 8+ messages in thread
From: Laurentiu Palcu @ 2025-07-09 12:23 UTC (permalink / raw)
To: imx, Laurentiu Palcu, Philipp Zabel, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: dri-devel, devicetree, linux-arm-kernel, linux-kernel
DCIF is the i.MX94 Display Controller Interface which is used to
drive a TFT LCD panel or connects to a display interface depending
on the chip configuration.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
.../bindings/display/imx/nxp,imx94-dcif.yaml | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
new file mode 100644
index 0000000000000..e4cab43c77ebc
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2025 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/nxp,imx94-dcif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX94 Display Control Interface (DCIF)
+
+maintainers:
+ - Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
+
+description:
+ The Display Control Interface(DCIF) is a system master that fetches graphics
+ stored in memory and displays them on a TFT LCD panel or connects to a
+ display interface depending on the chip configuration.
+
+properties:
+ compatible:
+ const: nxp,imx94-dcif
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description:
+ Interrupt output for CPU domain 0 (controlled by common registers group).
+ - description:
+ Interrupt output for CPU domain 1 (controlled by background layer registers group).
+ - description:
+ Interrupt output for CPU domain 2 (controlled by foreground layer registers group).
+
+ interrupt-names:
+ items:
+ - const: common
+ - const: bg_layer
+ - const: fg_layer
+
+ clocks:
+ items:
+ - description: APB bus clock
+ - description: AXI bus clock
+ - description: Pixel clock
+
+ clock-names:
+ items:
+ - const: apb
+ - const: axi
+ - const: pix
+
+ assigned-clocks:
+ description: Reference to DISPLAYMIX CSR clock mux.
+ maxItems: 1
+
+ assigned-clock-parents:
+ description: Parent of the clock mux.
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ nxp,blk-ctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle which points to NXP displaymix blk-ctrl.
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Display Pixel Interface(DPI) output port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ display-controller@4b120000 {
+ compatible = "nxp,imx94-dcif";
+ reg = <0x0 0x4b120000 0x0 0x300000>;
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common", "bg_layer", "fg_layer";
+ clocks = <&scmi_clk 69>, <&scmi_clk 70>, <&dispmix_csr 0>;
+ clock-names = "apb", "axi", "pix";
+ assigned-clocks = <&dispmix_csr 0>;
+ assigned-clock-parents = <&ldb_pll_pixel>;
+ power-domains = <&scmi_devpd 11>;
+ nxp,blk-ctrl = <&dispmix_csr>;
+
+ port {
+ dcif_out: endpoint {
+ remote-endpoint = <&ldb_in>;
+ };
+ };
+ };
+ };
--
2.46.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 5/8] dt-bindings: display: imx: Add bindings for i.MX94 DCIF
2025-07-09 12:23 ` [PATCH 5/8] dt-bindings: display: imx: Add bindings for i.MX94 DCIF Laurentiu Palcu
@ 2025-07-10 22:18 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2025-07-10 22:18 UTC (permalink / raw)
To: Laurentiu Palcu
Cc: imx, Philipp Zabel, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, dri-devel, devicetree,
linux-arm-kernel, linux-kernel
On Wed, Jul 09, 2025 at 03:23:24PM +0300, Laurentiu Palcu wrote:
> DCIF is the i.MX94 Display Controller Interface which is used to
> drive a TFT LCD panel or connects to a display interface depending
> on the chip configuration.
Drop 'bindings for' in the subject. You already said 'bindings' once.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> ---
> .../bindings/display/imx/nxp,imx94-dcif.yaml | 101 ++++++++++++++++++
> 1 file changed, 101 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
> new file mode 100644
> index 0000000000000..e4cab43c77ebc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
> @@ -0,0 +1,101 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2025 NXP
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/nxp,imx94-dcif.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX94 Display Control Interface (DCIF)
> +
> +maintainers:
> + - Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> +
> +description:
> + The Display Control Interface(DCIF) is a system master that fetches graphics
> + stored in memory and displays them on a TFT LCD panel or connects to a
> + display interface depending on the chip configuration.
> +
> +properties:
> + compatible:
> + const: nxp,imx94-dcif
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description:
> + Interrupt output for CPU domain 0 (controlled by common registers group).
> + - description:
> + Interrupt output for CPU domain 1 (controlled by background layer registers group).
> + - description:
> + Interrupt output for CPU domain 2 (controlled by foreground layer registers group).
> +
> + interrupt-names:
> + items:
> + - const: common
> + - const: bg_layer
> + - const: fg_layer
> +
> + clocks:
> + items:
> + - description: APB bus clock
> + - description: AXI bus clock
> + - description: Pixel clock
> +
> + clock-names:
> + items:
> + - const: apb
> + - const: axi
> + - const: pix
> +
> + assigned-clocks:
> + description: Reference to DISPLAYMIX CSR clock mux.
> + maxItems: 1
> +
> + assigned-clock-parents:
> + description: Parent of the clock mux.
> + maxItems: 1
You don't have to document assigned-clocks. Allowed anywhere with
'clocks'.
> +
> + power-domains:
> + maxItems: 1
> +
> + nxp,blk-ctrl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A phandle which points to NXP displaymix blk-ctrl.
> +
> + port:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Display Pixel Interface(DPI) output port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + display-controller@4b120000 {
> + compatible = "nxp,imx94-dcif";
> + reg = <0x0 0x4b120000 0x0 0x300000>;
> + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "common", "bg_layer", "fg_layer";
> + clocks = <&scmi_clk 69>, <&scmi_clk 70>, <&dispmix_csr 0>;
> + clock-names = "apb", "axi", "pix";
> + assigned-clocks = <&dispmix_csr 0>;
> + assigned-clock-parents = <&ldb_pll_pixel>;
> + power-domains = <&scmi_devpd 11>;
> + nxp,blk-ctrl = <&dispmix_csr>;
> +
> + port {
> + dcif_out: endpoint {
> + remote-endpoint = <&ldb_in>;
> + };
> + };
> + };
> + };
> --
> 2.46.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 7/8] arm64: dts: imx943-evk: Add support for DCIF and LVDS
2025-07-09 12:23 [PATCH 0/8] Add support for i.MX94 DCIF Laurentiu Palcu
2025-07-09 12:23 ` [PATCH 2/8] dt-bindings: display: fsl,ldb: Add binding for i.MX94 Laurentiu Palcu
2025-07-09 12:23 ` [PATCH 5/8] dt-bindings: display: imx: Add bindings for i.MX94 DCIF Laurentiu Palcu
@ 2025-07-09 12:23 ` Laurentiu Palcu
2025-07-11 5:07 ` Frank Li
2 siblings, 1 reply; 8+ messages in thread
From: Laurentiu Palcu @ 2025-07-09 12:23 UTC (permalink / raw)
To: imx, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: dri-devel, Laurentiu Palcu, devicetree, linux-arm-kernel,
linux-kernel
Add DT nodes for DCIF and LVDS in imx943.dtsi and activate them in
imx943-evk.dts.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/imx943-evk.dts | 126 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx943.dtsi | 56 ++++++++-
2 files changed, 181 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index c8c3eff9df1a2..e7de7ba406407 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -125,6 +125,132 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
device_type = "memory";
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&it6263_out>;
+ };
+ };
+ };
+};
+
+&dcif {
+ status = "okay";
+};
+
+&ldb {
+ assigned-clocks = <&scmi_clk IMX94_CLK_LDBPLL_VCO>,
+ <&scmi_clk IMX94_CLK_LDBPLL>;
+ assigned-clock-rates = <4158000000>, <1039500000>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ lvds_out: endpoint {
+ remote-endpoint = <&it6263_in>;
+ };
+ };
+ };
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pca9548_i2c3: i2c-mux@77 {
+ compatible = "nxp,pca9548";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds-to-hdmi-bridge@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ data-mapping = "jeida-24";
+ reset-gpios = <&pcal6416_i2c3_u171 8 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ it6263_in: endpoint {
+ remote-endpoint = <&lvds_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ it6263_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+ };
+
+ i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
&lpi2c3 {
diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 657c81b6016f2..db00a94812e18 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
@@ -148,7 +148,7 @@ l3_cache: l3-cache {
};
};
- clock-ldb-pll-div7 {
+ clock_ldb_pll_div7: clock-ldb-pll-div7 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
@@ -173,10 +173,64 @@ dispmix_csr: syscon@4b010000 {
lvds_csr: syscon@4b0c0000 {
compatible = "nxp,imx94-lvds-csr", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x0 0x4b0c0000 0x0 0x10000>;
clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
#clock-cells = <1>;
power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+
+ ldb: ldb@4 {
+ compatible = "fsl,imx94-ldb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4 0x4>, <0x8 0x4>;
+ reg-names = "ldb", "lvds";
+ clocks = <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>;
+ clock-names = "ldb";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_in: endpoint {
+ remote-endpoint = <&dcif_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+
+ dcif: display-controller@4b120000 {
+ compatible = "nxp,imx94-dcif";
+ reg = <0x0 0x4b120000 0x0 0x300000>;
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common", "bg_layer", "fg_layer";
+ clocks = <&scmi_clk IMX94_CLK_DISPAPB>,
+ <&scmi_clk IMX94_CLK_DISPAXI>,
+ <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
+ clock-names = "apb", "axi", "pix";
+ assigned-clocks = <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
+ assigned-clock-parents = <&clock_ldb_pll_div7>;
+ power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+ nxp,blk-ctrl = <&dispmix_csr>;
+ status = "disabled";
+
+ port {
+ dcif_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
};
};
};
--
2.46.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 7/8] arm64: dts: imx943-evk: Add support for DCIF and LVDS
2025-07-09 12:23 ` [PATCH 7/8] arm64: dts: imx943-evk: Add support for DCIF and LVDS Laurentiu Palcu
@ 2025-07-11 5:07 ` Frank Li
2025-07-15 12:05 ` Laurentiu Palcu
0 siblings, 1 reply; 8+ messages in thread
From: Frank Li @ 2025-07-11 5:07 UTC (permalink / raw)
To: Laurentiu Palcu
Cc: imx, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
On Wed, Jul 09, 2025 at 03:23:26PM +0300, Laurentiu Palcu wrote:
> Add DT nodes for DCIF and LVDS in imx943.dtsi and activate them in
> imx943-evk.dts.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx943-evk.dts | 126 +++++++++++++++++++
Shawn require board dts need sperate patch.
> arch/arm64/boot/dts/freescale/imx943.dtsi | 56 ++++++++-
> 2 files changed, 181 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> index c8c3eff9df1a2..e7de7ba406407 100644
> --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> @@ -125,6 +125,132 @@ memory@80000000 {
> reg = <0x0 0x80000000 0x0 0x80000000>;
> device_type = "memory";
> };
> +
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + label = "hdmi";
> + type = "a";
> +
> + port {
> + hdmi_connector_in: endpoint {
> + remote-endpoint = <&it6263_out>;
> + };
> + };
> + };
> +};
> +
> +&dcif {
> + status = "okay";
> +};
> +
> +&ldb {
> + assigned-clocks = <&scmi_clk IMX94_CLK_LDBPLL_VCO>,
> + <&scmi_clk IMX94_CLK_LDBPLL>;
> + assigned-clock-rates = <4158000000>, <1039500000>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
imx94.dts already set it
Frank
> +
> + port@1 {
> + reg = <1>;
> +
> + lvds_out: endpoint {
> + remote-endpoint = <&it6263_in>;
> + };
> + };
> + };
> +};
> +
> +&lpi2c3 {
> + clock-frequency = <400000>;
> + pinctrl-0 = <&pinctrl_lpi2c3>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + pca9548_i2c3: i2c-mux@77 {
> + compatible = "nxp,pca9548";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + lvds-to-hdmi-bridge@4c {
> + compatible = "ite,it6263";
> + reg = <0x4c>;
> + data-mapping = "jeida-24";
> + reset-gpios = <&pcal6416_i2c3_u171 8 GPIO_ACTIVE_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + it6263_in: endpoint {
> + remote-endpoint = <&lvds_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + it6263_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> + };
> + };
> +
> + i2c@4 {
> + reg = <4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@5 {
> + reg = <5>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@6 {
> + reg = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@7 {
> + reg = <7>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> };
>
> &lpi2c3 {
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index 657c81b6016f2..db00a94812e18 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> @@ -148,7 +148,7 @@ l3_cache: l3-cache {
> };
> };
>
> - clock-ldb-pll-div7 {
> + clock_ldb_pll_div7: clock-ldb-pll-div7 {
> compatible = "fixed-factor-clock";
> #clock-cells = <0>;
> clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> @@ -173,10 +173,64 @@ dispmix_csr: syscon@4b010000 {
>
> lvds_csr: syscon@4b0c0000 {
> compatible = "nxp,imx94-lvds-csr", "syscon";
> + #address-cells = <1>;
> + #size-cells = <1>;
> reg = <0x0 0x4b0c0000 0x0 0x10000>;
> clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> #clock-cells = <1>;
> power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +
> + ldb: ldb@4 {
> + compatible = "fsl,imx94-ldb";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4 0x4>, <0x8 0x4>;
> + reg-names = "ldb", "lvds";
> + clocks = <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>;
> + clock-names = "ldb";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lvds_in: endpoint {
> + remote-endpoint = <&dcif_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> + };
> +
> + dcif: display-controller@4b120000 {
> + compatible = "nxp,imx94-dcif";
> + reg = <0x0 0x4b120000 0x0 0x300000>;
> + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "common", "bg_layer", "fg_layer";
> + clocks = <&scmi_clk IMX94_CLK_DISPAPB>,
> + <&scmi_clk IMX94_CLK_DISPAXI>,
> + <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
> + clock-names = "apb", "axi", "pix";
> + assigned-clocks = <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
> + assigned-clock-parents = <&clock_ldb_pll_div7>;
> + power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> + nxp,blk-ctrl = <&dispmix_csr>;
> + status = "disabled";
> +
> + port {
> + dcif_out: endpoint {
> + remote-endpoint = <&lvds_in>;
> + };
> + };
> };
> };
> };
> --
> 2.46.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 7/8] arm64: dts: imx943-evk: Add support for DCIF and LVDS
2025-07-11 5:07 ` Frank Li
@ 2025-07-15 12:05 ` Laurentiu Palcu
0 siblings, 0 replies; 8+ messages in thread
From: Laurentiu Palcu @ 2025-07-15 12:05 UTC (permalink / raw)
To: Frank Li
Cc: imx, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
Hi Frank,
On Fri, Jul 11, 2025 at 01:07:06AM -0400, Frank Li wrote:
> On Wed, Jul 09, 2025 at 03:23:26PM +0300, Laurentiu Palcu wrote:
> > Add DT nodes for DCIF and LVDS in imx943.dtsi and activate them in
> > imx943-evk.dts.
> >
> > Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx943-evk.dts | 126 +++++++++++++++++++
>
> Shawn require board dts need sperate patch.
Ok, I'll create a patch for each file.
Thanks,
Laurentiu
>
> > arch/arm64/boot/dts/freescale/imx943.dtsi | 56 ++++++++-
> > 2 files changed, 181 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> > index c8c3eff9df1a2..e7de7ba406407 100644
> > --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> > @@ -125,6 +125,132 @@ memory@80000000 {
> > reg = <0x0 0x80000000 0x0 0x80000000>;
> > device_type = "memory";
> > };
> > +
> > + hdmi-connector {
> > + compatible = "hdmi-connector";
> > + label = "hdmi";
> > + type = "a";
> > +
> > + port {
> > + hdmi_connector_in: endpoint {
> > + remote-endpoint = <&it6263_out>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&dcif {
> > + status = "okay";
> > +};
> > +
> > +&ldb {
> > + assigned-clocks = <&scmi_clk IMX94_CLK_LDBPLL_VCO>,
> > + <&scmi_clk IMX94_CLK_LDBPLL>;
> > + assigned-clock-rates = <4158000000>, <1039500000>;
> > + status = "okay";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> imx94.dts already set it
>
> Frank
> > +
> > + port@1 {
> > + reg = <1>;
> > +
> > + lvds_out: endpoint {
> > + remote-endpoint = <&it6263_in>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&lpi2c3 {
> > + clock-frequency = <400000>;
> > + pinctrl-0 = <&pinctrl_lpi2c3>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + pca9548_i2c3: i2c-mux@77 {
> > + compatible = "nxp,pca9548";
> > + reg = <0x77>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + i2c@0 {
> > + reg = <0>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c@1 {
> > + reg = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c@2 {
> > + reg = <2>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c@3 {
> > + reg = <3>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + lvds-to-hdmi-bridge@4c {
> > + compatible = "ite,it6263";
> > + reg = <0x4c>;
> > + data-mapping = "jeida-24";
> > + reset-gpios = <&pcal6416_i2c3_u171 8 GPIO_ACTIVE_HIGH>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > +
> > + it6263_in: endpoint {
> > + remote-endpoint = <&lvds_out>;
> > + };
> > + };
> > +
> > + port@2 {
> > + reg = <2>;
> > +
> > + it6263_out: endpoint {
> > + remote-endpoint = <&hdmi_connector_in>;
> > + };
> > + };
> > + };
> > + };
> > + };
> > +
> > + i2c@4 {
> > + reg = <4>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c@5 {
> > + reg = <5>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c@6 {
> > + reg = <6>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c@7 {
> > + reg = <7>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > };
> >
> > &lpi2c3 {
> > diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> > index 657c81b6016f2..db00a94812e18 100644
> > --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> > @@ -148,7 +148,7 @@ l3_cache: l3-cache {
> > };
> > };
> >
> > - clock-ldb-pll-div7 {
> > + clock_ldb_pll_div7: clock-ldb-pll-div7 {
> > compatible = "fixed-factor-clock";
> > #clock-cells = <0>;
> > clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> > @@ -173,10 +173,64 @@ dispmix_csr: syscon@4b010000 {
> >
> > lvds_csr: syscon@4b0c0000 {
> > compatible = "nxp,imx94-lvds-csr", "syscon";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > reg = <0x0 0x4b0c0000 0x0 0x10000>;
> > clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> > #clock-cells = <1>;
> > power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> > +
> > + ldb: ldb@4 {
> > + compatible = "fsl,imx94-ldb";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x4 0x4>, <0x8 0x4>;
> > + reg-names = "ldb", "lvds";
> > + clocks = <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>;
> > + clock-names = "ldb";
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > +
> > + lvds_in: endpoint {
> > + remote-endpoint = <&dcif_out>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + dcif: display-controller@4b120000 {
> > + compatible = "nxp,imx94-dcif";
> > + reg = <0x0 0x4b120000 0x0 0x300000>;
> > + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "common", "bg_layer", "fg_layer";
> > + clocks = <&scmi_clk IMX94_CLK_DISPAPB>,
> > + <&scmi_clk IMX94_CLK_DISPAXI>,
> > + <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
> > + clock-names = "apb", "axi", "pix";
> > + assigned-clocks = <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
> > + assigned-clock-parents = <&clock_ldb_pll_div7>;
> > + power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> > + nxp,blk-ctrl = <&dispmix_csr>;
> > + status = "disabled";
> > +
> > + port {
> > + dcif_out: endpoint {
> > + remote-endpoint = <&lvds_in>;
> > + };
> > + };
> > };
> > };
> > };
> > --
> > 2.46.1
> >
^ permalink raw reply [flat|nested] 8+ messages in thread