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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm2314207f8f.34.2025.07.10.09.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:16:49 -0700 (PDT) From: Bryan O'Donoghue Subject: [PATCH 0/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver Date: Thu, 10 Jul 2025 17:16:46 +0100 Message-Id: <20250710-x1e-csi2-phy-v1-0-74acbb5b162b@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAG7nb2gC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDc0MD3QrDVN3k4kwj3YKMSt00MxNjkyQzU8MU40QloJaCotS0zAqwcdG xtbUASxDxul4AAAA= X-Change-ID: 20250710-x1e-csi2-phy-f6434b651d3a To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Bryan O'Donoghue , Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3679; i=bryan.odonoghue@linaro.org; h=from:subject:message-id; bh=09k8nauOQI+SPJuQ2FMg+lvL3iW+Ogwh/RRpwWFIjkc=; b=owEBbQKS/ZANAwAIASJxO7Ohjcg6AcsmYgBob+dwghGiTiZwUODkbb3BqmCZMxbX8rhID17lv e3N3Z1CtjWJAjMEAAEIAB0WIQTmk/sqq6Nt4Rerb7QicTuzoY3IOgUCaG/ncAAKCRAicTuzoY3I OrOqD/9kP6o7zHrhn9IppVvEfzzjSS6CG4hFOsGvB8sLItvuICt3F8CJOqCLRHRaLmEwdzLzw5I BCbuYebi4e4TcpD+ihirP3CUYJ1vMgBq4HVHK1E3LJ3DuityYMCJRuHBVsbPb4HYNDKSa0ocMAe eyghoWqK8PW/fRxgrLfY2c3JO3yVsBwRRXn40UCHZ8we5CgfDQ8GKTQhWJturXeE/QfW14JY9H5 JXAwTkzVAw/NNb0AUL4QsHDMslHv5FcOsXTdqzVuzrTcYwyVfoNkmY4BuZzFZjvwGefBbrlLHvF qX4g0luzZx4LOqtxVGwEp/wylhtYzQDKx9H7PJ5nWn+W74nySj8FAqRsQpOTfECqw4Vtg0HxYpV BewQjhfIakBxPs56w7R6mWWa/h+Tj4eNJbzpxU3Yqd54eQskzgO0OqD98MOl4hA1nLzRElgCSYG H4xcJKKJyUAEjPjwtovKJy2myujH8JfvuQKuo2cLeWR5eq6RftXaNOKsWVbquEPoFDjqx/1+j53 U565Yj5lhLsb7swxkY87Pkf5y16frcbZ701jrEciGAEwuQOygNb2tapF4eo0zEha6trJn9aKUUc LAzWu1/aWAuUVOhNr2GokB0HpobvfDDNKrwnmKm8gjxPQcVvHlPlxXpabrFARdniYpgpVigzZr7 8tJJDqzgJ90Nj5g== X-Developer-Key: i=bryan.odonoghue@linaro.org; a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A This short series adds a CSI2 MIPI PHY driver, initially supporting D-PHY mode. The core logic and init sequences come directly from CAMSS and are working on at least five separate x1e devices. The rationale to instantiate CSI2 PHYs as standalone devices instead of as sub-nodes of CAMSS is as follows. 1. Precedence CAMSS has a dedicated I2C bus called CCI Camera Control Interface. We model this controller as its own separate device in devicetree. This makes sense and CCI/I2C is a well defined bus type already modelled in Linux. MIPI CSI2 PHY devices similarly fit into a well defined separate bus/device structure. Contrast to another CAMSS component such as VFE, CSID or TPG these components only interact with other CAMSS inputs/outputs unlike CSIPHY which interacts with non-SoC components. 2. Hardware pinouts and rails The CSI2 PHY has its own data/clock lanes out from the SoC and indeed has its own incoming power-rails. 3. Other devicetree schemas There are several examples throughout the kernel of CSI PHYs modeled as standalone devices which one assumes follows the same reasoning as given above. I've been working on this on-and-off since the end of April: Link: https://lore.kernel.org/linux-media/c5cf0155-f839-4db9-b865-d39b56bb1e0a@linaro.org There is another proposal to have the PHYs be subdevices of CAMSS but, I believe we should go with a "full fat" PHY to match best practices in drivers/phy/qualcomm/*. Using the standard PHY API and the parameter passing that goes with it allows us to move away from custom interfaces in CAMSS and to conform more clearly to established PHY paradigms such as the QMP combo PHY. Looking at existing compat strings I settled on "qcom,x1e80100-mipi-csi2-combo-phy" deliberately omitting reference to the fact the PHY is built on a four nano-meter process node, which seems to match recent submissions to QMP PHY. My first pass at this driver included support for the old two phase devices: Link: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commit/a504c28d109296c93470340cfe7281231f573bcb#b6e59ed7db94c9da22e492bb03fcda6a4300983c I realised that the device tree schema changes required to support a comprehensive conversion of all CAMSS to this driver would be an almost certainly be unacceptable ABI break or at the very least an enormous amount of work and verification so I instead aimed to support just one new SoC in the submission. I've retained the callback indirections give us scope to add in another type of future PHY including potentially adding in the 2PH later on. This driver is tested and working on x1e/Hamoa and has been tested as not breaking sc8280xp/Makena and sm8250/Kona. Signed-off-by: Bryan O'Donoghue --- Bryan O'Donoghue (2): dt-bindings: phy: qcom: Add MIPI CSI2 C-PHY/DPHY Combo schema phy: qcom-mipi-csi2: Add a CSI2 MIPI D-PHY driver .../phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml | 95 ++++ MAINTAINERS | 11 + drivers/phy/qualcomm/Kconfig | 11 + drivers/phy/qualcomm/Makefile | 6 + drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 491 +++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 281 ++++++++++++ drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 101 +++++ 7 files changed, 996 insertions(+) --- base-commit: 2b0b621d5db55cf01bb200e6e6976b4ff4810544 change-id: 20250710-x1e-csi2-phy-f6434b651d3a Best regards, -- Bryan O'Donoghue