From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A742E2046A6; Fri, 11 Jul 2025 07:44:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752219846; cv=none; b=fbbCNjo0fRSdyPQTh844t5mQSIqN9C3lmwqehnMs9ao6UQUIR4XBQLwklK4j+822mtZDU7XlohIRj3Aau088vuQ5ky3z7j7M1RVpY2Dc/TNMrM8PlX2H4UI5LrKvIZaB3L0cqEbtE3/XM4VjsBKo4N8nNEXcp96LqWU8tDBXjY4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752219846; c=relaxed/simple; bh=4lgeUcntkB8hGROx3TWd47HBW0Gu/RzofzkzRiKszu4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=P7w0DMVlwvzVmxH3lTV3m/fKwlWAJB0c6mLI/k3kldpoLZDi6xoGiYJdY4jeU+dhQpimcrDPPPsbWKfmEUE8hqRE4d9/0gpDbi0yNaQPTsgXEcdV/T4crnbUVQeeyVDBkpYuXWFFHdXRg2B4INeG6QAAm6l/Bci6LcdbAt0TXOk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=K6gWwSiY; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="K6gWwSiY" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56B59Vu0019846; Fri, 11 Jul 2025 09:43:51 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= Cp2gFOEZRolrC1cu3ilAyN1wQaeSGonjrUSYtHJ5W+g=; b=K6gWwSiYbNkqYpoa QYaAjGONUeFIayYu742y4olXGmzwIVN13jSSfkHzPJzTuVv81cSxnGgDLCYyf5xb 9DEE25tJGeC1QVTRi0LJULrDnufmHv71k4Kzah3QRXgkMjK4TW/OW+OHbII10Nft PvJdMrfPssdval11VsaN2vIlrk4rL6h4dWfnOh5JlpsxIVNK7vlU2VaVFwYtMv02 vrq2J87SlIzR0Jmx9JbABjeGvXwX1DAfCvgMSskXVrur8ePogU+HYyqRdoWkd/up uQNi/bR/3AZgk/fmcxlil8cYhGL/+UOYAMMKF2dEL0cRlAoZOTpyB2muESCJ3rtZ M5GGGA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 47pud3ne9r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Jul 2025 09:43:51 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A00494004D; Fri, 11 Jul 2025 09:42:42 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 99ACBB157C6; Fri, 11 Jul 2025 09:41:40 +0200 (CEST) Received: from localhost (10.252.16.187) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 11 Jul 2025 09:41:40 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Fri, 11 Jul 2025 09:41:22 +0200 Subject: [PATCH v7 4/8] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp13 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-ID: <20250711-hdp-upstream-v7-4-faeecf7aaee1@foss.st.com> References: <20250711-hdp-upstream-v7-0-faeecf7aaee1@foss.st.com> In-Reply-To: <20250711-hdp-upstream-v7-0-faeecf7aaee1@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , Antonio Borneo , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-7616d X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-11_02,2025-07-09_01,2025-03-28_01 Add the hdp devicetree node for stm32mp13 SoC family. Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic --- arch/arm/boot/dts/st/stm32mp131.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 492bcf586361..7519ffa0dba8 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -954,6 +954,13 @@ dts: thermal@50028000 { status = "disabled"; }; + hdp: pinctrl@5002a000 { + compatible = "st,stm32mp131-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; -- 2.43.0