From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EC6A1EFFBB; Fri, 11 Jul 2025 07:43:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752219841; cv=none; b=ZFzhodpVJWlfghOjpALqNsPPzLsEjZ17kpIwGCnqlLXNCxDzMWjU1d2yoVcEIjAo6zgoDfMrnQ8ZtcxG616hOHyyVYn84YmpjMH+MpJCvSVKMeFoGIPpXkBIyzaLYPLVKqipdmC3bhQTTa/spWDh1+32R4aiCO+lsW9e3C01B1E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752219841; c=relaxed/simple; bh=lndg55ulgwz6N3tlL/yuiVojWKk/upndGowO0ds+dBM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=h7okSn0CxmVPKO3pkUj3nShCp+bTk/TdDLTxlZoMAW95LGiOmwGIqifgkGj9k/DvQqCaGCp2SgjzzseTDpbJwc5mP8MaADUVsUR5EZYy/pLs4UejNYpMO1rX2WpG2w7hqC1Lu6BMDgj2tj3QNdsUgRY9sW9MS7eKHRGUiM0DYSI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=knCdc4Il; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="knCdc4Il" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56B52O6J021363; Fri, 11 Jul 2025 09:43:46 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= dqAz444oyv1tNExXQ6LB+NGBTHbnGCQW3fM6rAo+GF0=; b=knCdc4IlckrjBG18 2mPI9uOryNcsstLUEu3o2IllKsq2jZMNInEK7Uv6+UitSAL+dZ2R0dBs6C7Fi6U/ y6mLrC+ISuXKqDfK0FgNPfCgSvpKxQScIgD6EQTw7U0sqVFY/8OB3fOUArTTCfqB QjspOeO9rW35Kx5kGm6YtwOugV5R9rMfXDqBhNkMVp0ClKkZBwbRHO+AzF5/qMTp 2yIFjPQ6dV5VlxMgebCYt/l8B3Rf4Ok8fVSj8wrN+QYB9s6pNG0coKydBaJk3AMO 5R8sFcNkBqvy6Lb5B8Z3RMiu/9+uUHyYLc+zt4Hld0VqhYgVSl1sC/EOcAp9PomB /TZGzw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 47pud3ne8s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Jul 2025 09:43:46 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id B4C4C40054; Fri, 11 Jul 2025 09:42:42 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 81732B1114C; Fri, 11 Jul 2025 09:41:41 +0200 (CEST) Received: from localhost (10.252.16.187) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 11 Jul 2025 09:41:41 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Fri, 11 Jul 2025 09:41:23 +0200 Subject: [PATCH v7 5/8] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp15 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-ID: <20250711-hdp-upstream-v7-5-faeecf7aaee1@foss.st.com> References: <20250711-hdp-upstream-v7-0-faeecf7aaee1@foss.st.com> In-Reply-To: <20250711-hdp-upstream-v7-0-faeecf7aaee1@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , Antonio Borneo , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-7616d X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-11_02,2025-07-09_01,2025-03-28_01 Add the hdp devicetree node for stm32mp15 SoC family Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic --- arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 0daa8ffe2ff5..b1b568dfd126 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -270,6 +270,13 @@ dts: thermal@50028000 { status = "disabled"; }; + hdp: pinctrl@5002a000 { + compatible = "st,stm32mp151-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + status = "disabled"; + }; + mdma1: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; -- 2.43.0